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 H ar d wa r e Re f er e n c e M a n u a l , D S 1 , F e b . 2 0 0 1
a D O F I (R)2 - C SwI. C w w
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Two Channel Codec m o F i l t e r w i t h P C M a nc .d M i c r o c o n t r o l l e r I4U e r f a c e nt
PE B 2 2 6 6 V e r sio n 2 .2 PE F 2 2 6 6 V e rsio n 2 .2
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Never stop
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Edition 2001-02-20 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2001.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
H ar d wa r e Ref er e n c e M a n u a l , D S 1 , F e b . 2 0 0 1
S I C O F I (R)2 - C Two Channel Codec Filter with PCM and Microcontroller Interface
PE B 2 2 6 6 V e r sio n 2 .2 PE F 2 2 6 6 V e rsio n 2 .2
Wired C om mu n i ca t i o n s
Never stop thinking.
PEB 2266 PEF 2266 Revision History: Previous Version:
Current Version 2001-02-20
Data Sheet 07.97 DS1 (V 1.1) Delta Sheet 11.98 DS2 (V 1.4) Errata Sheet 05.98 DS1 (V 1.4)
DS 1
Page
Subjects (major changes since last revision)
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
ABM(R), AOP(R), ARCOFI(R), ARCOFI(R)-BA, ARCOFI(R)-SP, DigiTape(R), EPIC(R)-1, EPIC(R)-S, ELIC(R), FALC(R)54, FALC(R)56, FALC(R)-E1, FALC(R)-LH, IDEC(R), IOM(R), IOM(R)-1, IOM(R)-2, IPAT(R)-2, ISAC(R)-P, ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P TE, ITAC(R), IWE(R), MUSAC(R)-A, OCTAT(R)-P, QUAT(R)-S, SICAT(R), SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R) are registered trademarks of Infineon Technologies AG. ACETM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUTTM are trademarks of Infineon Technologies AG.
PEB 2266 PEF 2266
Table of Contents Page
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 1.1 1.2 1.3 2 2.1 2.2 3 3.1 3.2 4 4.1 4.1.1 4.1.2 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.8.1 4.2.8.2 4.2.9 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15 4.2.16 4.2.17 4.2.18 5 5.1 5.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DSP-based Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Programming and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Power On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Overload Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 0 dBm0-Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Compressor Gain Relative to Coding Law . . . . . . . . . . . . . . . . . . . . . . . .15 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Gain Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Gain Tracking (Receive and Transmit) . . . . . . . . . . . . . . . . . . . . . . . . . .17 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Group Delay, Absolute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Group Delay Distortion with Frequency . . . . . . . . . . . . . . . . . . . . . . . .19 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Harmonic and Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . .20 Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Out-of-Band Discrimination in Transmit Direction . . . . . . . . . . . . . . . . . .23 Out-of-Band Discrimination in Receive Direction . . . . . . . . . . . . . . . . . . .24 Out-of-Band Idle Channel Noise at Analog Output . . . . . . . . . . . . . . . . .25 Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Coupling Capacitors at the Analog Interface . . . . . . . . . . . . . . . . . . . . . .27
Hardware Reference Manual
2001-02-20
PEB 2266 PEF 2266
Table of Contents 5.1.2 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.3.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 6 6.1 6.1.1 6.1.2 6.1.3 6.2 7 7.1 7.1.1 7.2 7.2.1 7.3 8 8.1 8.2 8.3 8.4.1 8.5 8.4 8.6 8.6.1 8.6.2 8.7 8.8 8.8.1 8.8.2 Page
Analog Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 PCM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 PCM Receive and Transmit Example . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Signaling Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Signaling Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Debouncing Functions and Interrupt Generation . . . . . . . . . . . . . . . . . . .33 Clock Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Serial Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Serial Microcontroller Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Three-Wire Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 CRAM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Types of Commands and Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Guidelines for Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Filter Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Proposal for SICOFI(R)2-C Board Design . . . . . . . . . . . . . . . . . . . . . . . . . .43 Electrical Characteristics and Timing Diagrams . . . . . . . . . . . . . . . . . .44 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Coupling Capacitors at the Analog Interface . . . . . . . . . . . . . . . . . . . . . .46 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 PCM-Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Single Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Double Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Signaling Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Timing from the C Interface to the SO/SB-pins . . . . . . . . . . . . . . . . . . .50 Timing from the SI/SB-pins to the C Interface . . . . . . . . . . . . . . . . . . . .50
Hardware Reference Manual
2001-02-20
PEB 2266 PEF 2266
Table of Contents 9 9.1 9.2 9.3 10 11 Page
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Analog Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Digital Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Cut-Off's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Hardware Reference Manual
2001-02-20
PEB 2266 PEF 2266
List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Page
SICOFI(R)2-C Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 SICOFI(R)2-C Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Configuration of SICOFI(R)2-C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 SICOFI(R)2-C Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 SICOFI(R)2-C State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Analog and PCM Signal Levels in A-Law Mode . . . . . . . . . . . . . . . . . .15 Analog and PCM Signal Levels in -Law Mode . . . . . . . . . . . . . . . . . . .15 Simplified Signal Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Total Distortion Measured with Sine-Wave, Receive and Transmit . . . .20 Total Distortion Receive (Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Total Distortion Transmit (Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Overload Compression (-Law Coding, Transmit Direction) . . . . . . . . .22 Out-of-Band Discrimination in Transmit Direction . . . . . . . . . . . . . . . . .23 Analog Output: Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Analog Output: Out-of-Band Idle Channel Noise . . . . . . . . . . . . . . . . . .25 Analog Interface to Two Subscriber Line Interface Circuits (SLICs) . . .28 PCM Interface Example: Location of Time Slots . . . . . . . . . . . . . . . . . .31 PCM Interface Example: Detail A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Signaling Example: Two Subscriber Lines. . . . . . . . . . . . . . . . . . . . . . .32 Serial Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Example for a Two-Byte Write Access. . . . . . . . . . . . . . . . . . . . . . . . . .35 Example for a One-Byte Read Access . . . . . . . . . . . . . . . . . . . . . . . . .35 Example for a Read Access with Byte-by-Byte Transfer . . . . . . . . . . . .36 Bi-Directional Data Signal: DIN and DOUT Strapped Together. . . . . . .36 Channel-Specific and Common Coefficients . . . . . . . . . . . . . . . . . . . . .39 Development System with STUT 2466 Evaluation Board . . . . . . . . . . .41 SICOFI(R)2-C Test Circuit Configuration . . . . . . . . . . . . . . . . . . . . . . . .42 Proposal for a Ground Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 PCM Interface Timing in Single Clocking Mode. . . . . . . . . . . . . . . . . . .47 PCM Interface Timing in Double Clocking Mode . . . . . . . . . . . . . . . . . .48 Timing of the Microcontroller Interface. . . . . . . . . . . . . . . . . . . . . . . . . .49 Signaling Output Timing (data downstream) . . . . . . . . . . . . . . . . . . . . .50 Analog Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Digital Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Cut-Off's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Hardware Reference Manual
2001-02-20
PEB 2266 PEF 2266
List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Page
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Register Values and Accessibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input and Output Pin Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Analog Voltage Levels Corresponding to 0 dBm0-Level . . . . . . . . . . . 14 Gain Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Gain Deviations with Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Attenuation with Frequency in Transmit and Receive Direction. . . . . . 18 Group Delay, Absolute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Group Delay Distortion with Frequency . . . . . . . . . . . . . . . . . . . . . . . . 19 Idle Channel Noise in Transmit Direction. . . . . . . . . . . . . . . . . . . . . . . 19 Idle Channel Noise in Receive Direction . . . . . . . . . . . . . . . . . . . . . . . 19 Harmonic and Intermodulation Distortion. . . . . . . . . . . . . . . . . . . . . . . 20 Signal-to-Total Distortion Ratio Measured with Sine Wave . . . . . . . . . 20 Signal-to-Total Distortion Ratio Measured with Noise . . . . . . . . . . . . . 21 Crosstalk Between Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Out-of-Band Signals Applied to the Analog Inputs (VINx) . . . . . . . . . . 23 Out-of-Band Signals at the Analog Outputs (VOUTx) . . . . . . . . . . . . . 24 Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Analog Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PCM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PCM Register Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . 30 Signaling Interface: Pins and Functions for SLIC Interfaces . . . . . . . . 33 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Serial Microcontroller Interface: Pins and Functions . . . . . . . . . . . . . . 34 Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Read Access to Common Configuration Register (XR) Map . . . . . . . . 38 Write Access to Common Configuration Register (XR) Map . . . . . . . . 38 Channel-Specific Configuration Register (CR) Map (Read & Write) . . 38 Coefficient RAM (CRAM) Structure per Channel . . . . . . . . . . . . . . . . . 39 Coefficient RAM (CRAM) Structure per Set . . . . . . . . . . . . . . . . . . . . . 40 Types of Commands and Data Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . 40 Analog Loop Programming in Register CR3, Bits 7 to 4 . . . . . . . . . . . 51 Digital Loop Programming in Register CR3, Bits 7 to 4 . . . . . . . . . . . . 52 Cut-Off Programming in Register CR2, Bits 7 to 5. . . . . . . . . . . . . . . . 53
Hardware Reference Manual
2001-02-20
PEB 2266 PEF 2266
Preface
This document provides detailed technical information about the SICOFI(R)2-C. It is intended for anyone considering or using the device for system design or board layout for a broad range of analog telephony applications. All content applies to both the standard PEB 2266 and the extended temperature version, PEF 2266, unless specified. Organization of this Document This Hardware Reference Manual is organized as follows: * Chapter 1, Overview Includes a general description of the architecture, feature list, and logic symbol. * Chapter 2, Pin Descriptions Illustrates the Pin Configuration and provides detailed functional descriptions. * Chapter 3, Functional Description Provides a block diagram and summarizes the major functional blocks. * Chapter 4, Operational Description Begins with a state diagram and description of the operating states of all two channels and concludes with detailed transmission characteristics. * Chapter 5, Interface Descriptions Describes the Analog, PCM, Signaling, and Serial Microcontroller interfaces. * Chapter 6, Programming Overview Illustrates the register model and coefficient RAM structure, provides a register map and summary, and identifies the programming command sequences. * Chapter 7, Application Hints Describes the development system available for the PEB 2266, and provides guidelines and schematics for board layout. * Chapter 8, Electrical Characteristics and Timing Diagrams Provides detailed tables for the electrical characteristics and includes timing diagrams for the Analog, PCM, Serial Microcontroller, and Signaling interfaces. * Chapter 9, Test Configuration Describes the test loops and cut-offs available for functional tests and diagnostics. * Chapter 10, Package Outlines Illustrates the P-MQFP-64 package in which the PEB 2266 is manufactured. * The Appendix Includes a glossary and an index. Related Documentation Other documentation for the PEB 2266 includes a Product Brief, a Product Overview, a Programmer's Reference Manual, and assorted Application Notes. Similar documentation is also available for the other members of the SICOFI Codec family including the PSB 2132, PSB 2134, and PEB 2466. Documentation is available by accessing our website: http://www.infineon.com/sicofi
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PEB 2266 PEF 2266
Overview
1
Overview
The two-channel codec filter PEB 2266 SICOFI(R)2-C is built around a central DSP-core which provides independent filter structures for all channels. Its analog I/O pins are used to connect to external subscriber line interface circuits (SLICs). Their signals are internally routed to the analog-to-digital and digital-to-analog converters (ADC, DAC). The signaling pins carry line status and control information to and from the SLICs. Two programmable clock outputs are available. The SICOFI(R)2-C connects to the digital switching and transmission system through two PCM Highways. The digitized voice band signals are available as A-Law or -Law codes within selectable 8-bit time slots. The SICOFI(R)2-C modes, features, and filter characteristics are programmed through a serial interface to a microcontroller. The access mechanism is very simple, and can be implemented with as few as three I/O ports. The PEB 2266 is available for standard temperature range applications (0 C to +70 C); the PEF 2266 is available for extended temperature range applications (-40 C to +85 C).
PEB 2266 SICOFI2-C
t/r SLIC 1 ADC - DAC Signaling ADC - DAC Signaling
DSP Core
Digital Filters Channel 1 PCM Interface Highway A
t/r
SLIC 2
Digital Filters Channel 2
Highway B
PLL, Clocking
Status and Control Registers
CRAM
Serial Microcontroller Interface
2266_201
Figure 1
SICOFI(R)2-C Architecture
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Two Channel Codec Filter with PCM and Microcontroller Interface SICOFI(R)2-C
PEB 2266 PEF 2266
Version 2.2
CMOS
1.1
Features
* Two-channel single chip codec with digital filters * High analog driving capability (300 , 50 pF) for direct driving of transformers * Digital Signal Processing (DSP) technique * Programmable digital filters to adapt transmission behavior, especially for: - AC impedance matching P-MQFP-64 - Transhybrid balancing - Frequency response - Signal levels - A/-Law compression and expansion * Fulfills international (e.g. ITU-T Q.552, G.712) and country-specific requirements * High performance ADC and DAC for excellent linearity and dynamic gain * Programmable Analog Interface to electronic SLICs or transformer solutions * Seven SLIC-signaling I/O pins per channel with programmable debouncing * Two PCM Highways accessible by on-chip PCM Interface with Programmable time slot assignment and variable data rates from 128 kbit/s to 8 Mbit/s * Easy to use 4-pin Serial Microcontroller Interface (SPI compatible) for read/write access * Single supply voltage (5 V) * Advanced low-power mixed-signal CMOS technology * Two programmable tone generators (DTMF possible) * Level metering function for system tests and for analog input signal testing * Advanced on-chip functions for device and system diagnostics and manufacturing test - Five digital loops - Four analog loops * Support tools include: - Hardware development board -- STUT 2466 - QSICOS Coefficient Calculation and Register Configuration Software * Standard P-MQFP-64 package Type PEB 2266 Version 2.2 PEF 2266 Version 2.2
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Package P-MQFP-64 P-MQFP-64
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PEB 2266 PEF 2266
Overview
1.2
Logic Symbol
Analog Interface
Channel 1 Channel 2
VIN1 VOUT1 VIN2 VOUT2 DRA DXA TCA#
CHCLK1 CHCLK2 SI1_0 SI1_1 SO1_0 SO1_1 SB1_0 SB1_1 SB1_2 SI2_0 SI2_1 SO2_0 SO2_1 SB2_0 SB2_1 SB2_2 INT12 RESET#
Highway A Highway B PCM Clocks Master Clock PCM Interface
SICOFI(R)2-C PEB 2266
DRB DXB TCB# FSC PCLK
Channel 1 Signaling Interface Ch. 1&2 Channel 2
MCLK
DOUT DIN DCLK CS#
2266_203
Microcontroller Interface
Figure 2
SICOFI(R)2-C Logic Symbol
1.3
Typical Applications
Many applications will benefit from the versatility of the SICOFI(R)2-C codec and filter. The inherent flexibility enables several products to be developed around one basic architecture, thus affording potentially significant savings in time to market, inventory costs, and support administration. The following list represents some of the typical applications for which the SICOFI(R)2-C codec was designed: Analog linecards for Central Offices and PBXs, Small PBX or Key Systems, Digital Loop Carrier (DLC) Systems, Digital Added Main Lines (DAML) Systems, Pair-Gain Systems, Fiber-to-the-Curb (FTTC) Systems, Radio-in-the-Loop (RITL) Systems, and any Multi-channel, digital voice processing, storage, or communication applications. Refer to the Product Overview, Chapter 5 Application Hints for more information.
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Pin Descriptions
2
2.1
Pin Descriptions
Pin Diagram
(top view) P-MQFP-64
SI2_1 SI2_0 SB2_2 SB2_1 SB2_0 SO2_1 SO2_0 SO1_0 SO1_1 SB1_0 SB1_1 SB1_2 SI1_0 SI1_1 INT12 CHCLK1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VIN1 GNDA1 VOUT1 VDDA12 VOUT2 GNDA2 VIN2 VREF VDDREF NC GNDA NC VDDA NC GNDA NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PCLK FSC DRB DXB TCB# DRA DXA TCA# VDDD RESET# MCLK GNDD DOUT DIN DCLK CS#
SICOFI(R)2-C PEB 2266-H
6
78
9 10 11 12 13 14 15 16 NUI NC CHCLK2
NUI NUI NUIO NUIO NUIO NC NC NC NC NUIO NUIO NUIO NUI
2266_204
Figure 3
Pin Configuration of SICOFI(R)2-C
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PEB 2266 PEF 2266
Pin Descriptions
2.2
Table 1
Pin Definitions and Functions
Pin Definitions and Functions Ch.
Pin Symbol Type Function 1, 2 NUI I I/O Non Usable Input Pins tie directly to digital ground (Pin 21) Non Usable Input/Output Pins tie via a pull-down-resistor to digital ground (Pin 21) Not Connected Pins not connected in this device. I/O Non Usable Input/Output Pins tie via a pull-down-resistor to digital ground (Pin 21) Non Usable Input Pins tie directly to digital ground (Pin 21) Not Connected Pins not connected in this device. O I Chopper Clock Output 2 Provides 256, 512, or 16,384 kHz signal; sync. to MCLK. Chip Select Microcontroller Interface chip select, enable to read or write; active low. Data Clock Microcontroller Interface data clock, shifts data from or to device; maximum clock rate 8192 kHz. Data Input Microcontroller Interface control data input pin; DCLK determines data rate. Data Output Microcontroller Interface control data output pin; DCLK determines data rate: DOUT is high impedance "Z" if no data is transmitted from the SICOFI(R)2-C. Digital Ground Ground reference for all digital signals. Internally isolated from GNDA1 (Pin 50), GNDA2 (Pin 54), and GNDA (Pins 59 and 63).
3, 4, NUIO 5 6, 7, NC 8, 9 10, 11, 12 13, 14 15 16 17 NUIO
NUI NC CHCLK2 CS#
I
both both
18
DCLK
I
both
19
DIN
I
both
20
DOUT
O
both
21
GNDD
I
both
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Pin Descriptions Pin Symbol Type Function 22 MCLK I Master Clock Input 1536, 2048, 4096 or 8192 kHz must be applied for any operation (selected in Register XR5). MCLK, PCLK, FSC must be synchronous. Reset Input Forces the device to default setting mode; active low. Ch. both
23 24 25
RESET#
I I O
both
VDDD
TCA#
Digital Supply Voltage both +5 V supply for digital circuits (use 100 nF blocking cap.). Transmit Control Output A PCM Interface: active if data is transmitted via DXA; active low, open drain. Data Transmit to PCM-Highway A PCM Interface: PCM data for each channel is transmitted in 8-bit bursts every 125 s. Data Receive from PCM-Highway A PCM Interface: PCM data for each channel is received in 8-bit bursts every 125 s. Transmit Control Output B PCM Interface: active if data is transmitted via DXB; active low, open drain. Data Transmit to PCM-Highway B PCM Interface: data for each channel is transmitted in 8-bit bursts every 125 s. Data Receive from PCM-highway B PCM Interface: data for each channel is received in 8-bit bursts every 125 s. Frame Synchronization Clock 8 kHz; reference for individual time slots, indicates start of PCM frame; MCLK, PCLK, FSC must be synchronous. PCM Data Clock 128 to 8192 kHz; determines the rate at which PCM data is shifted into or out of the PCM-ports. MCLK, PCLK, FSC must be synchronous. Chopper Clock Output 1 Provides programmable (2 ... 28 ms) output signal (synchronous to MCLK). both
26
DXA
O
both
27
DRA
I
both
28
TCB#
O
both
29
DXB
O
both
30
DRB
I
both
31
FSC
I
both
32
PCLK
I
both
33
CHCLK1
O
both
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Pin Descriptions Pin Symbol Type Function 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 INT12 SI1_1 SI1_0 SB1_2 SB1_1 SB1_0 SO1_1 SO1_0 SO2_0 SO2_1 SB2_0 SB2_1 SB2_2 SI2_0 SI2_1 O I I I/O I/O I/O O O O O I/O I/O I/O I I I I O Interrupt Output, Channels 1 and 2 Active high. Signaling Input Channel 1, Pin 1 Signaling Input Channel 1, Pin 0 Bi-directional Signaling, Channel 1 Pin 2 Bi-directional Signaling, Channel 1 Pin 1 Bi-directional Signaling, Channel 1 Pin 0 Signaling Output, Channel 1, Pin 1 Signaling Output, Channel 1, Pin 0 Signaling Output, Channel 2, Pin 0 Signaling Output, Channel 2, Pin 1 Bi-directional Signaling, Channel 2 Pin 0 Bi-directional Signaling, Channel 2 Pin 1 Bi-directional Signaling, Channel 2 Pin 2 Signaling Input, Channel 2, Pin 0 Signaling Input, Channel 2, Pin 1 Analog Voice (Voltage) Input, Channel 1 Requires a coupling capacitor >39 nF to the SLIC. Analog Ground, Channel 1 Not internally connected to GNDD or GNDA2 or GNDA. Analog Voice (Voltage) Output, Channel 1 Requires a coupling capacitor to the SLIC. The capacitor value depends on the SLIC's input impedance. (See Chapter 5.1, "Analog Interface" on page 27). Analog Supply Voltage, Channels 1 and 2 +5 V (100 nF blocking capacitor required). Analog Voice (Voltage) Output, Channel 2 Requires a coupling capacitor to the SLIC. The capacitor value depends on the SLIC's input impedance. (See Chapter 5.1, "Analog Interface" on page 27). Analog Ground, Channel 2 Not internally connected to GNDD or GNDA1 or GNDA. Analog Voice (Voltage) Input, Channel 2 Requires a coupling capacitor >39 nF to the SLIC. Ch. both 1 1 1 1 1 1 1 2 2 2 2 2 2 2 1 1 1
VIN1
GNDA1
VOUT1
52 53
VDDA12 VOUT2
I O
both 2
54 55
GNDA2
I I
2 2
VIN2
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Pin Descriptions Pin Symbol Type Function 56 57 58 59 Ch. both both
VREF VDDREF
NC GNDA
I/O I
Reference Voltage Must connect to a 220 nF cap. to ground. Analog Supply Reference Voltage +5 V (100 nF blocking capacitor required). Not Connected Pin not connected in this device.
I
Analog Ground Internally isolated from GNDD (Pin 21), GNDA1(Pin 50), and GNDA2 (Pin 54). Not Connected Pin not connected in this device.
60 61 62 63
NC
VDDA
NC GNDA
I
Analog Supply Voltage +5 V (100 nF blocking capacitor required). Not Connected Pin not connected in this device.
I
Analog Ground Internally isolated from GNDD (Pin 21), GNDA1(Pin 50), and GNDA2 (Pin 54). Not Connected Pin not connected in this device.
64
NC
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Functional Description
3
Functional Description
The telephone subscriber loop is a bi-directional two-wire line. The Subscriber Line Interface Circuit (SLIC) on the network side converts the two-wire interface to a four-wire interface which communicates with the SICOFI(R)2-C via separate receive and transmit signals, VIN and VOUT. The SLIC can be either a transformer or an electronic circuit with operational amplifiers. It must have a defined input impedance towards the subscriber line for maximum signal power transfer and return loss. The requirements for the input impedance vary from country to country and demand impedance matching to the different environments. Country-specific adaptations are also required for the transhybrid loss, which is a loss between the transmit and the receive ports of the twowire to four-wire hybrid.
3.1
DSP-based Architecture
The impedance matching and transhybrid balancing functions are performed by loop filters between the transmit path (analog to PCM) and the receive path (PCM to analog). The filter characteristics must be adjusted according to the local requirements of each market. In the analog domain, filters must be optimized in hardware; this is generally both tedious and time-consuming. This is not the case with the DSP-based SICOFI(R)2C two-channel codec. Its integrated signal processor implements the impedance matching and transhybrid balancing functions as digital, programmable filters. It also performs frequency response corrections and level adjustments to enable the design of a truly universal and internationally applicable telephone linecard. Transmission characteristics and frequency behavior are enhanced by the accuracy of the digital filters, which do not fluctuate over temperature or with age. As an additional benefit of its DSP-based architecture, the PEB 2266 also provides two tone generators per channel. An on-chip level-metering unit allows line-characterization without extra hardware; it can also be used to detect specific tones, e.g., modem tones.
3.2
Programming and Control
A very simple Microcontroller Interface is used to program the SICOFI(R)2-C functions. The same port provides access to 14 general purpose I/O pins of the Signaling Interface. This allows efficient and convenient monitoring and control of other linecard functions, such as on-/off-hook detection, ground-key detection, switching of ring signals and test relays. The Serial Microcontroller Interface provides a programming and control interface and is generic and non-proprietary for use with any microcontroller. It can be implemented with as few as three signal lines, since the data receive and data transmit pins may be strapped together.
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Functional Description Figure 4 SICOFI(R)2-C Block Diagram
Highway A Programmable Filters and Gain A-Law or -Law A-Law or -Law Compander PCMInterface with Time Slot Assignment DXA DRA TCA# FSC PCLK DXB DRB TCB# Highway B
PEB 2266, SICOFI2-C VIN1 VOUT1 VIN2 VOUT2 MCLK CHCLK1 CHCLK2 SIx_y SOx_y SBx_y Signaling Interface Serial Microcontroller Interface ADC DAC ADC DAC Hardware Filters
Hardware Filters
Programmable Filters and Gain Digital Signal Processing
PLL, Clocking Registers and CRAM
INT12
DCLK
CS#
DIN
DOUT
2266_205
Figure 4 shows the functional blocks and the interface pins of the SICOFI(R)2-C: * Two independent bi-directional voice channels; * Oversampling sigma-delta A/D and D/A converters with excellent resolution, dynamic range, linearity, accuracy and signal-to-noise performance; * Hardware filters for decimation and interpolation of the ADC and DAC bit stream, and pre-processing of the voice data to reduce the load of the DSP; * DSP core with programmable, channel-independent filter structures for impedance matching, transhybrid balancing, frequency correction and level adjustments; * Configurable A-Law or -Law compressor and expander units; * Two PCM port with data rates from 128 kbps to 8 Mbps per highway; * Programmable time slot assignment for each channel; * Fourteen signaling input and output pins, accessible through registers; * On-chip PLL for an internal 16,384 kHz clock; * Two programmable versatile clock outputs; * Eight common configuration registers (XR-Registers) affecting all two channels; * Two sets of six channel-specific registers (CR-Registers); and * Coefficient RAM (CRAM) for filter coefficients storage for each channel.
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Operational Description
4
Operational Description
Each channel of the SICOFI(R)2-C can be in one of two stable states: "Standby" and "Operating". These states can be switched by programming Bit 0 (PU) in the channel-specific configuration register CR1. "Standby" is a power-saving state. Keeping any unused channels in this state reduces the overall system power dissipation. The third state, "Reset", is transient and is reached after applying power to the device (Power On), after asserting a logic low signal to the RESET#-pin (HW-Reset), or after issuing an XOP command with Bit 7 (RST) set to "1" (SW-Reset). Both channels would be affected in any case.
4.1
Operating States
Power-On HW-Reset SW-Reset
Reset (both channels)
Standby Ch.1 Power Down Ch.1
Standby Ch.2 Power Down Ch.2
Power Up Ch.1 Operating Ch.1
Power Up Ch.2 Operating Ch.2
2266_206
Figure 5
SICOFI(R)2-C State Diagram
4.1.1
Power On
All input pins must be at GND level before applying VDD to the SICOFI(R)2-C. Otherwise, the device may not enter the Reset State. In this case, the SICOFI(R)2-C can be reset by HW- or SW-Reset, or can be initialized by setting all registers to zero.
4.1.2
Hardware Reset
Voltage levels lower than 1.2 V applied to Pin 23 (RESET#) for more than 3 s will reset the SICOFI(R)2-C. Spikes that are shorter than 1 s will be ignored. When RESET# is released the SICOFI(R)2-C will enter Standby State.
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Operational Description Table 2 Register Values and Accessibility SICOFI(R)2-C State Reset 00H 00H unchanged Standby user configurable user configurable user configurable Operating user configurable user configurable user configurable
Register CR0 ... CR4 XR0 ... XR7 CRAM Table 3 Pin DIN DOUT DRA, DRB DXA, DXB TCA#, TCB# VOUT1 , VOUT2 VIN1 , VIN2 SBx_y SOx_y SIx_y CHCLK1 CHCLK2 Table 4
Input and Output Pin Behavior SICOFI(R)2-C State Reset ignored high impedance ignored high impedance high high impedance ignored configured as input GNDD ignored high high Power Dissipation Typical Power Dissipation 2.5 mW 70 mW 90 mW Standby serial input serial output ignored high impedance high high impedance ignored programmable as input or output digital output digital input programmable frequency programmable freq. (not 16,384 kHz) Operating serial input serial output active receive time slot active transmit time slot low during active transmit time slot analog output analog input programmable as input or output digital output digital input programmable frequency programmable frequency
No. of Channels Operating None 1 2
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Operational Description
4.2 4.2.1
Transmission Characteristics Overload Point
The overload point of the SICOFI(R)2-C A/D converters is at 2.223 V. This is the peak amplitude of a sine wave level of 1.572 Vrms. Higher input signal levels will be distorted. Theoretical load capacities for A-Law and -Law encoded signals are defined in ITU-T Recommendation G.711. These values correspond to the SICOFI(R)2-C overload point: Table 5 Maximum Signal Levels PCM Interface Encoding Law A-Law -Law Theoretical Load Capacity (according to ITU-T G.711) 3.14 dBm0 3.17 dBm0 Analog Interface Max. Sine Wave Level (SICOFI(R)2-C Overload Point) 1.572 Vrms
4.2.2
0 dBm0-Levels
The analog voltage levels corresponding to a 0 dBm0 sine wave signal can be calculated from the maximum signal levels shown in Table 5. The results are shown in Table 6. Table 6 Analog Voltage Levels Corresponding to 0 dBm0-Level Analog Sine Wave Level corresponding to 0 dBm0 PCM Level 1.572 Vrms*10^(-3.14/20) = 1.095 V rms 1.572 Vrms*10^(-3.17/20) = 1.091 V rms
Encoding Law A-Law -Law
Note: Periodic PCM codes for a 1 kHz sine wave signal with 0 dBm0 level can be found in ITU-T G.711.
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Operational Description
4.2.3
Compressor Gain Relative to Coding Law
The -Law compressor unit of the SICOFI(R)2-C automatically adds 1.94 dB gain, which has to be considered for the total gain calculation. The accumulated gain of all programmable transmit filters (AX1+AX2+FRX) must not exceed 7 dB if the device is set to -Law operation. If the device is set to A-Law operation, then the accumulated gain must not exceed 9 dB.
Transmit
1014 Hz 1.095 Vrms
VIN
A/D
0 dB Gain
A-Law Compressor
DXA/B
0 dBm0
VOUT 1.095 Vrms
D/A
0 dB Gain
A-Law Expander
DXA/B
1014 Hz 0 dBm0
Receive
2266_207
Figure 6
Analog and PCM Signal Levels in A-Law Mode
Transmit -Law Compressor [+1.94 dB]
1014 Hz 1.091 Vrms
VIN
A/D
0 dB Gain
DXA/B
1.94 dBm0
VOUT 1.091 Vrms
D/A
0 dB Gain
-Law Expander
DXA/B
1014 Hz 0 dBm0
Receive
2266_208
Figure 7
Analog and PCM Signal Levels in -Law Mode
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Operational Description
4.2.4
Operating Conditions
The specifications to which the SICOFI(R)2-C are tested are tighter than the ITU-T Q.552 Specification to guardband various SLIC implementations. The guaranteed transmission characteristics of the SICOFI(R)2-C under test conditions ensure that the final linecard design will meet the ITU-T specification. The figures in this document are based on the subscriber-line board requirements. Proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) requires a complete knowledge of the analog environment in which the SICOFI(R)2-C is to be used. Unless otherwise stated, the transmission characteristics are guaranteed within the following operating conditions: * * * * * * * * *
TA = 0 C to 70 C (PEB 2266), TA = -40 C to 85 C (PEF 2266); VDD = 5 V 5%;
GNDA1,2,3,4 = GNDD = 0 V; Load on VOUT: RL > 300 ; CL < 50 pF; H(IM) = H(TH) = 0; H(R1) = H(FRX) = H(FRR) = 1; HPR and HPX enabled; AR = 0 to -9 dB (AR = AR1 + AR2 + FRR + R1); AX = 0 to +9 dB for A-Law, AX = 0 to +7 dB for -Law (AX = AX1 + AX2 + FRX); * f = 1014 Hz; 0 dBm0; A-Law or -Law; * AGX = 0 dB, +6.02 dB; and * AGR = 0 dB, -6.02 dB.
Transmit Path Analog AGX Input ADC AX2 FRX AX1 HPX CMP PCM Output
IM
TH
Analog AGR Output Receive Path DAC R1 AR2 FRR AR1 HPR EXP
PCM Input
2266_209
Figure 8
Simplified Signal Flow Diagram
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Operational Description
4.2.5
Table 7
Gain Accuracy
Gain Accuracy Symbol Limit Values min. typ. max. Unit dB dB dB dB Test Conditions
Parameter Absolute Gain Variation with Temperature Variation with Supply Voltage Variation with Analog Gain
G
-0.20 0.10 +0.20 0.05 0.05 0.05
TA = 25 C,VDD = 5 V,
AGX = AGR = 0 dB
TA = -40 C to 85 C VDD = 5 V 5%
AGX= +6.02 dB, AGR= -6.02 dB
4.2.6
Gain Tracking (Receive and Transmit)
The gain deviation for a 1014 Hz sine-wave input signal will stay within limits shown in Table 8. All values are relative to the gain of a 0 dBm0 input signal. Table 8 Input Level -55 to -50 dBm0 -50 to -37 dBm0 -37 to 3 dBm0 Gain Deviations with Input Level Symbol G G G Gain Deviation min. typ. max. 1.4 0.5 0.25 Unit dB dB dB Test Conditions 1014 Hz sine-wave test signal. Reference level is at 0 dBm0.
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Operational Description
4.2.7
Table 9
Frequency Response
Attenuation with Frequency in Transmit and Receive Direction Receive Loss min. 0 0 -0.125 -0.125 -0.125 -0.125 0 0.3 0.65 max. Transmit Loss min. >2 0 -0.125 0.125 -0.125 -0.125 -0.125 0 1 0.125 0.3 0.65 max. Unit dB dB dB dB dB dB dB Test Conditions 0 dBm0 input signal level. 1014 Hz reference frequency
Input Frequency 0 Hz to 100 Hz 100 Hz to 200 Hz 200 Hz to 300 Hz 300 Hz to 3.0 kHz 3.0 kHz to 3.2 kHz 3.2 kHz to 3.4 kHz > 3.4 kHz
4.2.8 4.2.8.1
Group Delay Group Delay, Absolute Values
Table 10 shows the limit values for the Absolute Group Delay. The maximum delays are valid when the SICOFI(R)2-C is operating with H(TH) = H(IM) = 0, and H(FRR) = H(FRX) = 1, and include the delay through the A/D and D/A converters. The typical delays are the average of all different time slot delays during one PCM frame. Table 10 Parameter Transmit Delay Receive Delay Group Delay, Absolute Values Symbol Limit Values min. 300 300 typ. 375 375 max. 450 450 Unit s s Test Conditions 0 dBm0 input signal level, fTest at TGmin.
DXA DRA
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Operational Description
4.2.8.2
Group Delay Distortion with Frequency
The Group Delay Distortion in transmit and receive direction will stay within the limits shown in Table 11. Group Delay Distortion values are referenced to the minimum value of Group Delay (TGmin). Table 11 Frequency 500 Hz to 600 Hz 600 Hz to 1.0 kHz 1.0 kHz to 2.6 kHz 2.6 kHz to 3.0 kHz Group Delay Distortion with Frequency Symbol tG tG tG tG Limit Values min. typ. max. 300 150 100 300 s s s s 0 dBm0 input signal level, reference point is at TGmin. Unit Test Conditions
4.2.9
Table 12
Noise
Idle Channel Noise in Transmit Direction Symbol Limit Values min. typ. max. -67.4 17.5 17.5 Unit dBm0p dBmc dBrnC0
Parameter A-Law, psophometric (VIN = 0 V) -Law, C-message (VIN = 0 V) -Law, C-message (VIN = 0 V) Table 13 Parameter A-Law, psophometric (idle code + 0) -Law, C-message (idle code + 0) -Law, C-message (idle code + 0)
NTP NTC NTC
Idle Channel Noise in Receive Direction Symbol Limit Values min. typ. -85 5 5 max. -78.0 12.0 12.0 Unit dBm0p dBmc dBrnC0
NRP NRC NRC
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Operational Description
4.2.10
Table 14
Harmonic and Intermodulation Distortion
Harmonic and Intermodulation Distortion Symbol Limit Values min. typ. -50 max. -44 Unit dB Test Conditions 0 dBm0; f = 1014 Hz Equal-level, 4-tone method (EIA-464) at composite level of -13 dBm0; f = 300 Hz to 3400 Hz
Parameter Harmonic Distortion 2nd, 3rd order Intermodulation
HD
R2 R3
IMD IMD
-46 -56
dB dB
4.2.11
Table 15
Total Distortion
Signal-to-Total Distortion Ratio Measured with Sine Wave Min. Values A-Law 24.5 29.5 35.5 36.4 -Law 27 31 35.5 36.4 Unit dB dB dB dB Test Conditions sine wave f=1014 Hz, receive and transmit, -Law: C-message weighted, A-Law: psophometrically weighted.
Input Level Symbol -45 dB -40 dB -30 dB > -28 dB S/D S/D S/D S/D
40 dB 30 27 24.5 35.5 31 29.5 36.4
-Law
A-Law
S/D
20
10
0 -60
-50
-45
-40
-30 -28
-20 Input Level
-10 dBm0 0
2266_210
Figure 9
Total Distortion Measured with Sine-Wave, Receive and Transmit
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Operational Description Table 16 Input Level -55 dB -40 dB -34 dB -27 dB -24 to -6 dB -3 dB
40 dB 30 36.7 34.3 29.7 36 28.4
Signal-to-Total Distortion Ratio Measured with Noise Symbol S/D S/D S/D S/D S/D S/D Min. Value, PEB 2266 Min. Value, PEF 2266 Receive 14.7 29.7 34.3 36 36.7 28.4 Transmit 13.7 28.7 33.3 35.4 36.3 27.4 Receive 14.7 29.7 34.3 36 36.7 28.4 Transmit 12 27 33.3 35.4 36.3 27.4 Unit dB dB dB dB dB dB
S/D
20 14.7 10
0 -60
-55
-50
-40
-34 -30 -24 -20 dBm0 -10 0 -27 -6 -3 Input Level
2266_211
Figure 10
Total Distortion Receive (Noise)
40 dB
33.3
35.4
36.3
30
27.0
28.7
27.4
PEB 2266
S/D
20
13.7 12
PEF 2266
10
0 -60
-55
-50
-40
-34
-30 -27
-24
-20 dBm0 -10
-6
-3
0
2266_212
Input Level
Figure 11
Total Distortion Transmit (Noise)
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Operational Description
4.2.12
Single Frequency Distortion
Frequency Range 300 Hz to 3.4kHz 0 Hz to 12 kHz max. Input Level 0 dBm0 0 dBm0
Test Input Signal Receive Direction Transmit Direction
Any resulting signal with a frequency different from the test input signal will stay at least 28 dB below the input signal level.
4.2.13
Overload Compression
This is measured with a 1014 Hz sine-wave signal. The overload point in -Law Mode is at 3.17 dBm0.
10 dBm0 8 7 6 5 4 3 2 1 0.25 0 -0.25 -1 Fundamental Output Power
0
1
2
3
4
5
6
7
dBm0
9
2266_213
Fundamental Input Power
Figure 12
Overload Compression (-Law Coding, Transmit Direction)
4.2.14
Table 17
Crosstalk
Crosstalk Between Channels Symbol Limit Values min. typ. - 85 max. - 80 Unit dB Test Conditions
Parameter Crosstalk, 0dBm0
CT
f = 200 Hz to 3400 Hz,
any combination of directions and channels
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Operational Description
4.2.15
Out-of-Band Discrimination in Transmit Direction
With any 0 dBm0 sine-wave signal below 100 Hz and in the range from 3.4 kHz to 100 kHz (out-of-band signal) applied to an analog input (VINx), the level of any resulting frequency component at the digital output will stay at least X dB (see Table 18) below the output level of a 0 dBm0 1kHz sine-wave reference signal at the analog input. Table 18 Out-of-Band Signals Applied to the Analog Inputs (VINx) Min. Output Signal Rejection X 25 10 4000 - f - 14 sin -------------------- - 1 1200 15 4000 - f - 18 sin -------------------- - 7 - 1200 9 40 Unit dB dB dB Test Conditions 0 dBm0 sine-wave input signal on VIN
Input Frequency 0 Hz to 60 Hz 60 Hz to 100 Hz 3.4 kHz to 4 kHz 4 kHz 4 kHz to 4.6 kHz 4.6 kHz to 100 kHz
dB dB
dB
The Hardware Filters behind the A/D Converters reject teletax pulses with their poles at 12 kHz 150 Hz and 16 kHz 150 Hz.
40 dB 32 30 Transmit Out-of-Band Discrimination X 25 20 15 10
0
0
0.06 0.1
3.4
4
4.6
6
10 f
18 kHz 100
2266_214
Figure 13
Out-of-Band Discrimination in Transmit Direction
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Operational Description
4.2.16
Out-of-Band Discrimination in Receive Direction
With any 0 dBm0 sine-wave frequency in the range from 300 Hz to 3.99 kHz applied to the digital input (PCM time slot), the level of any resulting out-of-band signal at the analog output will stay at least X dB (see Table 19) below the output level of a 0 dBm0 1kHz sine-wave reference signal at the digital input. Table 19 Out-of-Band Signals at the Analog Outputs (VOUTx) Min. Output Signal Rejection X 4000 - f - 14 sin -------------------- - 1 1200 f - 4600 35 + 22 -------------------5950 15 28 57 Unit dB Test Conditions 0 dBm0 sine-wave input signal on digital input (PCM time slot)
Output Frequency
3.4 kHz to 4.6 kHz
dB
4.6 kHz to 10.55 kHz 4 kHz 4.6 kHz >10.55 kHz
dB dB dB
60 dB 50 Receive Out-of-Band Discrimination X 40 35 30 20 15 10 0
57
28
0
0.06 0.1
3.4
4
4.6
6
16 18 kHz 100 8 10 2266_215 10.55 f
Figure 14
Analog Output: Out-of-Band Signals
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Operational Description
4.2.17
Out-of-Band Idle Channel Noise at Analog Output
With an idle code (any sequence of constant PCM octets) applied to the digital input, the level of any resulting out-of-band power spectral density at the analog output, measured with 3 kHz bandwidth, will be not greater than the limit curve shown in Figure 15.
-40 dBm0 -50 -55 -60
Out of Band Noise
-70 -78 -80 -90 -100 1 10
2 3 4
10
10
kHz f
10
2266_216
Figure 15
Analog Output: Out-of-Band Idle Channel Noise
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Operational Description
4.2.18
Transhybrid Loss
The quality of Transhybrid-Balancing is very sensitive to deviations in gain, group delay, and deviations inherent to the A/D- and D/A-converters, as well as to all external components used on a linecard (SLIC, OP's etc.). Transhybrid loss test setup: The SICOFI(R)2-C test loop "DLB-ANA" is selected (see Figure 34), which connects the analog output with the analog input. The programmable filters FRR, AR, FRX, AX are by-passed. The IM-filter is disabled, (H(IM)=0). The balancing filter TH is enabled with optimized coefficients for this configuration (VOUT = VIN). A 0 dBm0 sine wave signal with a frequency in the range of 300 Hz to 3400 Hz is applied to the digital input. The signal levels of the resulting echo at the digital output will stay below the values shown in Table 20. Table 20 Transhybrid Loss Symbol Transhybrid Loss min. 27 30 29 27 27 typ. 40 45 40 35 35 Unit dB dB dB dB dB Test Condition
Input Frequency 300 Hz 500 Hz 2500 Hz 3000 Hz 3400 Hz
THL300 THL500 THL2500 THL3000 THL3400
TA = 25 C; VDD = 5 V
AGX = AGR = 0 dB; typical variation of amplitude: 0.15 dB delay: 0.5 s.
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Interface Description
5
* * * *
Interface Description
Analog Interface, PCM Interface, Signaling Interface, and Serial Microcontroller Interface.
The SICOFI(R)2-C provides four interfaces:
A general description of these interface is given in the Product Overview, Chapter 4. Refer to the Programmers Reference Manual for information on the configuration and operation of the four interfaces. The subsequent chapters in this manual explain how to connect the SICOFI(R)2-C to subscriber line interface circuits (SLICs), microcontrollers, and PCM highways.
5.1
Analog Interface
The Analog Interface in combination with a Subscriber Line Interface Circuit (SLIC) forms a configurable tip & ring (t/r) telephone line. The AC transmission characteristic of the SICOFI(R)2-C--SLIC combination can be controlled by programming the digital filter structures inside the SICOFI(R)2-C. The correct filter coefficients are determined by the targeted AC transmission behavior (e.g. Telco specification) and by the transfer functions of the SLIC. The SICOFI(R)2-C can be interfaced directly to electronic SLICs or transformer solutions. The high driving capability of up to 300 Ohms eliminates the need for an external amplifier that is normally used with transformer SLICs. The peak amplitude of the analog inputs and outputs is at 2.223 V (overload point). Out-of-band signals applied to the analog inputs are suppressed by the on-chip digital hardware filters. The poles of these filters are fixed at 12 kHz and 16 kHz which suppresses the echo signal from teletax pulses very efficiently: As long as the amplitude of the teletax echo stays below the overload threshold of 2.223 Vp (1.57 Vrms), the voice signal in the transmit path will not be disturbed. Thus, the on-chip hardware filters can eliminate the need for external teletax filters.
5.1.1
Coupling Capacitors at the Analog Interface
A coupling capacitor >39 nF must be used on the VIN-pins in the transmit direction. The required value for the coupling capacitor on the VOUT-pins depends on the input resistance of the SLIC-circuitry (RLoad). It has to be chosen to fulfil the frequency response requirement in the receive direction. Figure 16 can be used to determine an appropriate value for the coupling capacitor (CExt1).
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Interface Description
52
VDDA12 SLIC 1
100nF 50 > 39nF 49 51 CExt1
Channel 1 Channel 2 GNDA1 VIN1 VOUT1 GNDA2 54 VIN2
55
100nF
SLIC 2
t/r
RLoad
> 39nF
RLoad
t/r
VOUT2 53
CExt1
SICOFI2-C
VREF
56 220nF
VDDREF
100nF 57
10 2 F CExt1 1 10
CExt1=
1 fmin*RLoad
10
0
10 -1
fmin = 250 Hz
10
-2
10 -3 2 10
10
3
10
4
10
5
RLoad
10
6
2266_217
Figure 16
Analog Interface to Two Subscriber Line Interface Circuits (SLICs)
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5.1.2
Table 21
Analog Interface Pins
Analog Interface Pins Pin 49 Function Analog Input. Requires a coupling capacitor >39 nF to the SLIC (see Figure 16). Analog Output. Requires a coupling capacitor to the SLIC. The capacitor's value depends on the input impedance of the SLIC, (see Figure 16). Analog Ground. Internally isolated from GNDD, GNDA, or GNDA2. Analog Input. Requires a coupling capacitor >39 nF to the SLIC (see Figure 16). Analog Output. Requires a coupling capacitor to the SLIC. The capacitor's value depends on the input impedance of the SLIC, (see Figure 16). Analog Ground. Internally isolated from GNDD, GNDA, or GNDA2. Analog Supply Voltage. +5 V (100 nF blocking capacitor required, see Figure 16). Analog Supply Reference Voltage. +5 V (100 nF blocking capacitor required, see Figure 16). Reference Voltage Must connect to a 220 nF cap. to ground, see Figure 16.
Channel Symbol VIN1
VOUT1
51
GNDA1
50
VIN2
55
VOUT2
53
GNDA2 VDDA12 VDDREF VREF
54 52 57 56
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Interface Description
5.2
PCM Interface
The SICOFI(R)2-C provides an industry-standard PCM Interface with access to one PCM highways. The PCM Interface has the following features: * * * * * * * * Data rate from 128 kbit/s to 8 Mbit/s per highway, 2 to 128 time slots per frame per highway, PCM data format serialized 8 bits with MSB first, Configurable A-Law or -Law coding, Independently configurable time slot and highway for each channel and direction, PCM clock speed of once or twice the bit rates, Programmable sampling slopes, and Programmable frame delay.
5.2.1
Table 22 Symbol PCLK FSC DRA DRB DXA DXB TCA# TCB#
PCM Interface Pins
PCM Interface Pins Pin 32 31 27 30 26 29 25 28 Function PCM-Clock, 128 kHz to 8192 kHz; shared for both highways. Frame Synchronization Clock, 8 kHz; shared for both highways. Receive Data input for PCM-highway A. Receive Data input for PCM-highway B. Transmit Data output for PCM-highway A, open drain. Transmit Data output for PCM-highway B, open drain. Transmit Control output for highway A, low when DXA is active. Transmit Control output for highway B, low when DXB is active.
5.2.2
PCM Receive and Transmit Example
Figure 17 and Figure 19 illustrate the time slot and bit positions resulting from the programming example below: Table 23 Channel 1 2 all PCM Register Configuration Example CR4 0000 0000 0000 1111 Receive Setting DRA, time slot 0 DRA, time slot 15 CR5 0000 0000 0001 0010 Transmit Setting DXA, time slot 0 DXA, time slot 18
XR6=0000 0000; single clock mode, no PCM offset; PCLK=2048 kHz.
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Interface Description
125 s
FSC
PCLK 0123 DRA 0 DXA High 'Z' 18 High 'Z' Time Slot 15 31
TCA# Detail A
2266_218
Figure 17
PCM Interface Example: Location of Time Slots
FSC Clock 0 PCLK 1 2 3 4 5 6 7
DRA Bit 7 DXA High 'Z' 6
Voice Data 5 4 3 2 1 0 High 'Z'
Voice Data
TCA#
2266_219
Figure 18
PCM Interface Example: Detail A
The pins DRA/B and DXA/B may be strapped together to form a multiplexed bi-directional PCM port.
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Interface Description
5.3
Signaling Interface
The SICOFI(R)2-C Signaling Interface is used to monitor and control supervision and signaling functions on up to four subscriber lines. The device generates interrupt signals to indicate signaling status changes on any of the input pins. The Signaling Interface consists of the following I/O pins and functions: * 14 signaling pins (2 input pins, 2 output pins, and 3 user-configurable bi-directional pins per channel), * Debouncing functions, * 1 interrupts (one for each channel-pair), and * 2 clock output signals (user configurable).
5.3.1
Signaling Interface Pins
SICOFI2-C
33
CHCLK1
CHCLK2
16
SLIC 1 t/r Operating Mode Off-Hook Det. Ground Key Det. Ring Relay Status LED
39 38 37 36 35 41 40
Channel 1 Channel 2 SB1_0 SB1_1 SB1_2 SI1_0 SI1_1 SO1_0 SO1_1 INT 12
34
SLIC 2
44 45 46 47 48 42 43
SB2_0 SB2_1 SB2_2 SI2_0 SI2_1 SO2_0 SO2_1
Operating Mode Off-Hook Det. Ground Key Det. Ring Relay Status LED
t/r
Microcontroller
2266_220
Figure 19
Signaling Example: Two Subscriber Lines
Subscriber Lines
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Interface Description Table 24 Signaling Interface: Pins and Functions for SLIC Interfaces Channel 1 Pin 36 35 41 40 39 38 37 34 Symbol Function SI1_0 SI1_1 SO1_0 SO1_1 SB1_0 SB1_1 SB1_2 INT12 Signaling Input 0 Signaling Input 1 Signaling Output 0 Signaling Output 1 Bi-directional Signaling 0 Bi-directional Signaling 1 Bi-directional Signaling 2 47 48 42 43 44 45 46 SI2_0 SI2_1 SO2_0 SO2_1 SB2_0 SB2_1 SB2_2 Channel 2 Pin Symbol Function Signaling Input 0 Signaling Input 1 Signaling Output 0 Signaling Output 1 Bi-directional Signaling 0 Bi-directional Signaling 1 Bi-directional Signaling 2
Interrupt Output, Channels 1+2, active high
5.3.2
Debouncing Functions and Interrupt Generation
All signaling inputs are sampled at programmable intervals (Field N in register XR4). If all the inputs assigned to one channel-pair (1&2) have been stable for two subsequent samples their values are stored in the signaling registers and the associated interrupt output (INT12) is set high. Refer to the Programmer's Reference Manual for further details on this function.
5.3.3
Clock Output Signals
Two programmable Chopper Clock Output signals are provided by the PEB 2266: * CHCLK1 (Pin 33) is configured in register XR4.Field T (bits XR4.3 to XR4.0) * CHCLK2 (Pin 16) is configured in register XR5.CHCLK2 (bits XR5.3 and XR5.2) * Both Chopper Clock Output signals are only available if a valid Master Clock signal is applied to pin MCLK. * CHCLK2 = 16,384 kHz: Requires at least one channel in POWER-UP state. Table 25 Clock Programming CHCLK1 XR4.Field T 0000 0001 to 1110 1111 Output (Pin 33) High level (+5V) Clock period = T *2ms (min. 2 ms, max. 28 ms) Low level (0V) 00 01 10 11 CHCLK2 XR5.CHCLK2 Output (Pin 16) High level (+5V) 512 kHz signal 256 kHz signal 16,384 kHz signal
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Interface Description
5.4
Serial Microcontroller Interface
The Serial Microcontroller Interface is used to access the SICOFI(R)2-C's internal registers and the Coefficient RAM (CRAM). The Serial Microcontroller Interface consists of four pins: two data pins (DIN, DOUT), one clock pin (DCLK) and one pin for chip select (CS#). If DIN and DOUT are strapped together, only three microcontroller I/O pins are required to build this interface. Figure 20 Serial Microcontroller Interface
SICOFI2-C
CS# DCLK DIN DOUT
SICOFI2-C
CS# DCLK DIN DOUT
Out
Out
Out
In
Out
Out
I/O
Microcontroller
Microcontroller
Configuration A: Separate DIN, DOUT
Configuration B: Bi-Directional Data
2266_221
5.4.1
Table 26 Symbol CS# DCLK DIN DOUT
Serial Microcontroller Interface Pins
Serial Microcontroller Interface: Pins and Functions Pin 17 18 19 20 Function Chip Select, enable to read or write data, active low. Data Clock, shifts data from or to device; max. clock rate is 8192 kHz. Control Data Input; sampled with rising edge of DCLK. Control Data Output; bits are shifted with the falling edge of DCLK; DOUT is in high impedance state when no data is transmitted from the SICOFI(R)2-C.
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Interface Description
5.4.2
Write Access
Following a falling edge of CS#, the first eight bits received on DIN specify the type of command. The data bytes following a write command are stored in the selected configuration registers or the selected part of the Coefficient RAM. The number of data bytes depends on the type of command. After every command CS# must be set to '1'.
.
CS#
DCLK
DIN
765432107654321076543210 Write Command Data Byte 1 High 'Z'
2266_222
Data Byte 2
DOUT
Figure 21
Example for a Two-Byte Write Access
5.4.3
Read Access
If the first eight bits received via DIN represent a read command, the SICOFI(R)2-C will initiate its response via DOUT. An identification byte (81H) is followed by the requested number of data bytes (contents of configuration registers or contents of the CRAM). During execution of a read command, the device will ignore data on DIN. After every command CS# must be set to '1'.
.
CS#
DCLK
DIN
76543210 Read Command
DOUT
High 'Z'
7654321076543210 Identification 81H Data Byte 1
High 'Z'
2266_223
Figure 22
Example for a One-Byte Read Access
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Interface Description For byte-by-byte transfer, the high time of DCLK can be prolonged, resulting in a user-defined `waiting time' between bytes. This mechanism can be used for writing to and reading from the device.
CS#
DCLK
DIN
76543210 Read Command
DOUT
High 'Z' 7654321 Identification 81H 0 76543210 Data Byte 1
High 'Z'
2266_224
Figure 23
Example for a Read Access with Byte-by-Byte Transfer
Read and write commands can be chained by leaving CS# low after the completion of each command sequence. For read or write access to individual registers, the command sequence may be terminated by rising CS# after the transmission of any number of bytes.
5.4.4
Three-Wire Access
DIN and DOUT may be strapped together and connected to a single I/O pin of the microcontroller. The interface remains fully functional with only three wire connections. After every command CS# must be set to '1'.
CS#
DCLK
DATA
765432107654321076543210 Read Command Identification 81H Data Byte 1
High 'Z'
2266_225
Figure 24
Bi-Directional Data Signal: DIN and DOUT Strapped Together
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Programming Overview
6
Programming Overview
The transmission characteristics and interfaces of the PEB 2266 can be adapted to various environments. Configuring the functional blocks and programming the digital filter behavior is accomplished by loading values to the Configuration Registers and the Coefficient RAM (CRAM). Software utilities are available to determine the appropriate register and CRAM values (see Programmer's Reference Manual).
6.1
Programming Overview
The SICOFI(R)2-C has eight Common Configuration Registers (XR0 to XR7). Settings in these registers affect all two channels. Each of the two channels has six Channel-Specific Configuration Registers (CR0 to CR5). Settings in these registers affect only the designated channel. The filters of each channel are individually programmable through channel-specific coefficients in CRAM. There are two global sets of TH Filter coefficients that can be assigned to any channel.
6.1.1
Register Model
Channel-specific and Common Configuration Registers and coefficients are shown in Table 27. Table 27 Register Model Configuration Registers and CRAM XR0 to XR7 (8 bytes) CR0 to CR5 (6 bytes) IM/R1 Coefficients (16 bytes) FRR, FRX Coefficients (16 bytes) AR1, AR2, AX1, and AX2 Coefficients (8 bytes) TG1 and TG2 Coefficients (8 bytes) TH Coefficient Set 1 (24 bytes) TH Coefficient Set 2 (24 bytes) one coefficient set per channel channel-specific Channel Usage common
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Programming Overview
6.1.2
Table 28
Register Maps
Read Access to Common Configuration Register (XR) Map Bit 7 Bit 6 0 0 0 0 Bit 5 0 0 0 SB2_2 CRSH-A R-S OF5 Bit 4 0 0 0 SB1_2 CRSH-B DRV_0 OF4 Bit 3 SI2_1 SB2_1 PSB2_1 0 CHCLK2 Shift OF3 OF2 OF1 Bit 2 SI2_0 SB2_0 PSB2_0 0 Bit 1 SI1_1 SB1_1 PSB1_1 PSB2_2 CHCLK1 Version PCM-OFFSET OF0 Bit 0 SI1_0 SB1_0 PSB1_0 PSB1_2
XR0 XR1 XR2 XR3 XR4 XR5 XR6 XR7 Table 29
0 0 0 0
Signal Debounce MCLK-SEL C-Mode OF7 X-S OF6
Write Access to Common Configuration Register (XR) Map Bit 7 Bit 6 0 0 0 0 Bit 5 0 0 0 SB2_2 CRSH-A R-S OF5 Bit 4 0 0 0 SB1_2 CRSH-B DRV_0 OF4 Bit 3 SO2_1 SB2_1 PSB2_1 0 CHCLK2 Shift OF3 OF2 OF1 Bit 2 SO2_0 SB2_0 PSB2_0 0 Bit 1 SO1_1 SB1_1 PSB1_1 PSB2_2 CHCLK1 Version PCM-OFFSET OF0 Bit 0 SO1_0 SB1_0 PSB1_0 PSB1_2
XR0 XR1 XR2 XR3 XR4 XR5 XR6 XR7 Table 30
0 0 0 0
Signal Debounce MCLK-SEL C-Mode OF7 X-S OF6
Channel-Specific Configuration Register (CR) Map (Read & Write) Bit 7 Bit 6 IM/R1 ETG1 COT/R TEST-Loops Bit 5 FRX PTG2 Bit 4 FRR PTG1 0 RS5 XS5 RS4 XS4 Bit 3 AX LAW IDR AGX RS3 XS3 Bit 2 AR 0 LM AGR RS2 XS2 0 LMR D-HPX RS1 XS1 Bit 1 Bit 0 PU V+T D-HPR RS0 XS0
CR0 CR1 CR2 CR3 CR4 CR5
TH ETG2
TH-SEL
R-way X-way
RS6 XS6
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Programming Overview
6.1.3
CRAM Structure
Coefficient RAM (CRAM) is used to store the individual coefficients calculated for each channel. The coefficients can be written and read through the Microcontroller Interface. The IM, FRX, FRR, AX, AR, TG1, TG2, and TH coefficients are accessed through the Coefficient Operation (COP) Command Sequences which include the channel address (see Programmer's Reference Manual Chapter 6.5). Channel-specific coefficients always belong to their designated channel. Common coefficients (TH) can be assigned to any of the two channels through field TH-SEL in CR0 (see Figure 25).
Common Coefficients Channel 1
IM Part 1 & 2, FRX, FRR, AX, AR, TG1, TG2
Channel 2 Set 1 Set 2
TH Part TH Part 1, 2, 3 1, 2, 3 IM Part 1 & 2, FRX, FRR, AX, AR, TG1, TG2
Channel Specific Coefficients
Channel Specific Coefficients
2266_226
Figure 25 Table 31 IM Part 1 IM Part 2 FRX FRR AX AR TG1 TG2
Channel-Specific and Common Coefficients Coefficient RAM (CRAM) Structure per Channel 8 Coefficient Bytes 8 Coefficient Bytes 8 Coefficient Bytes 8 Coefficient Bytes 4 Coefficient Bytes 4 Coefficient Bytes 4 Coefficient Bytes 4 Coefficient Bytes
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Programming Overview Table 32 TH Part 1 TH Part 2 TH Part 3 Coefficient RAM (CRAM) Structure per Set 8 Coefficient Bytes 8 Coefficient Bytes 8 Coefficient Bytes
6.2
Types of Commands and Data Bytes
Coefficients and register contents are programmed and accessed through command sequences via the Microcontroller Interface. There are three types of command sequences: * Extended Operation (XOP) for access to the Common Configuration Registers (XR0 to XR7) including the Control Registers for the signaling interface. * Status Operation (SOP) for access to the Channel-Specific Registers (CR0 to CR5), e.g. enabling and disabling of filters, time slot assignment, and test loops. * Coefficient Operation (COP) for access to the CRAM structures. Coefficients can be written to the SICOFI(R)2-C, and also read back. Table 33 Types of Commands and Data Bytes. 7 XOP SOP COP RST AD AD 6 0 5 RW RW RW 4 1 1 0 3 1 0 2 1 LSEL LSEL CODE 0
With the first byte received via DIN, a command type is selected through bits 3 and 4. A two-bit address field (AD) in the COP and SOP commands allows access to the channel-specific structures (CRAM and CR registers). Since the XR Registers are common for all channels, no address field is required within the XOP command byte. All three commands allow read and write access, which is indicated by bit 5 (RW). The bit fields LSEL and CODE specify the type and the length of data that follows the command.
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Application Hints
7
7.1 7.1.1
Application Hints
Support Tools Development Board
The Evaluation Package EASY 2466 includes the following hardware: * One SICOFI(R)2-C Evaluation Board STUT 2466 with connectors for four optional SLIC daughter cards and BNC connectors to a PCM backplane. * One microcontroller board EVC50x with RS-232 interface that translates data from a PC to SICOFI(R)2-C format. * Two SLIC Babyboards STUT 5502 with HARRIS SLIC HC 5502 mounted. The QSICOS software enables the calculation of the coefficients and the download of the setup file to the evaluation board. This setup allows measurements and optimization of the actual behavior of a complete transmission system. The EASY 2466 evaluation system connects directly to industry-standard test equipment.
tip ring
Power Supply
COM 1
SLIC (STUT5502)
SLC1 ST2 ST3
PC
reset EVC
sw1 P4
SLC2
SLC3
STUT 2466
PCM
out SLC4 S1 in
PCLK FSC
in/ out in/ out
FSC in
ST1
SICOFI2/4 -C/-TE
SICOFIx -C/-TE Eval. Board V1.4
Evaluation Board EVC50x
PC M in
PC M ou t
C lo ck ou t
4 wire in
2 w ire
4 w ire ou t
PCM-4
DC Loop-Holding circuit
Figure 26
Development System with STUT 2466 Evaluation Board
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Application Hints
7.2 7.2.1
Guidelines for Board Design Filter Capacitors
* For high frequency noise rejection, use 100 nF SMD ceramic capacitors on pins VDDA12, VDDA and VDDREF and connect to GNDA. Additional 2.2 F tantalum capacitors are recommended. * Use one 100 nF SMD ceramic capacitor on pin VDDD and connect to GNDD. * Use a 1 F - 10 F tantalum capacitor from +5 V supply to GND (central blocking). Note: All blocking capacitors MUST be placed as close as possible to the SICOFI(R)2-C pins.
.
Signaling Interface, Channels 1&2
5 x 680K 5 x 680K
48 Analog Interface
10F
33 SI2_1 SI2_0 SB2_2 SB2_1 SB2_0 SO2_1 SO2_0 SO1_0 SO1_1 SB1_0 SB1_1 SB1_2 SI1_0 SI1_1 INT12 CHCLK1 PCM Interface 32 5V
49
2.2F 100nF
VIN1 GNDA1 VOUT1 VDDA12 VOUT2 GNDA2 VIN2 VREF VDDREF NC GNDA NC VDDA NC GNDA NC
1F 5V 10F 2.2F 100nF 220nF 5V 2.2F 100nF
1F
SICOFI2-C PEB 2266-H
100nF 5V 100nF
64
1
6 x 680K
PCLK 4.7K FSC DRB 5V DXB 4.7K TCB# DRA DXA 5V TCA# 100nF 1-10F VDDD RESET# 10K MCLK GNDD DOUT DIN DCLK CS# 17 Microcontroller Interface 16
NUI NUI NUIO NUIO NUIO NC NC NC NC NUIO NUIO NUIO NUI NUI NC CHCLK2
2266_228
Figure 27
SICOFI 2-C Test Circuit Configuration
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PEB 2266 PEF 2266
Application Hints
7.3
Proposal for SICOFI(R)2-C Board Design
For a new layout design it is recommended to use a separate ground-layer which gives the possibilty to connect all ground-pins of the SICOFI(R)2-C (GNDA and GNDD) lowohmic together. Furthermore, an optimum board layout should follow these recommendations * * * * Separate all digital supply lines from analog supply lines as far as possible Applying the standard practice regarding blocking capacitors is recommended Place all SLIC circuits as close as possible to the Vinx/Voutx pins of the SICOFI Separate all analog circuitry (especially SLIC and Vinx/Voutx) as far as possible from any digital signal source (esp. clock signals)
The ground-plane should be used for shielding
100 nF Ceramic
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 33 15 34 14 35 13 36 SICOFI2-C V2.2 12 37 11 38 10 39 Ground9 40 plane 8 41 7 42 6 43 PEB 2266 H 5 44 4 45 3 46 2 47 1 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
GNDD
VDDD
VDD
Connector
1-10 F Tantal
next to the connector pins
GND
Connector
VREF VDDREF
VDDA12
GNDA1
GNDA2
GNDA
V DDA
GNDA
100 nF Ceramic
220 nF 100 nF Ceramic
100 nF Ceramic
Figure 28
Proposal for a Ground Concept
VDD is the grey colored layer and the Ground-plane is the black colored layer. The Ground-plane should be on both sides of the board on the top and on the ground layer.
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Electrical Characteristics and Timing Diagrams
8
8.1
Electrical Characteristics and Timing Diagrams
Absolute Maximum Ratings
Parameter Symbol Limit Values min. -0.3 -0.6 -5.3 -0.3 -0.3 -5.3 max. 7.0 0.6 0.3 5.3 5.3 0.3 10 Unit V V V V V V mA C C W Test Condition
VDD referred to GNDD
GNDA to GNDD Analog input and output voltage Referred to VDD = 5 V; Referred to GNDA = 0 V All digital input voltages Referred to GNDD = 0 V; (VDD = 5V) Referred to VDD = 5 V; (GNDD = 0 V) DC input and output current at any input or output pin (free from latch-up) Storage temperature Ambient temperature under bias Power dissipation (package)
TSTG TA PD
-60 -10
125 80 1
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Electrical Characteristics and Timing Diagrams
8.2
Operating Range
VDD = 5 V 5%; GNDD = 0 V; GNDA = 0 V; TA = 0 C to +70 C (PEF 2266: -40 C to +85 C)
Parameter Symbol Limit Values min. typ. max. 0.5 0.5 14 18 1.0 1.5 25 30 Unit Test Condition FSC = 8 kHz, mA PCLK = MCLK = mA 2.048 MHz, mA no loads, mA PCM idle codes, dB Ripple: sine wave 1014 Hz, 70 mVrms, on every supply pin, AGX=AGR=AX=AR=0dB (see Chapter 4.2.4)
VDD supply current:
Standby (PEB 2266) Standby (PEF 2266) 1 channel operating 2 channels operating Power supply rejection ratio (either direction)
IDD
PSRR
30
8.3
Digital Interface
VDD = 5 V 5%; GNDD = 0 V; GNDA = 0 V TA = 0 C to +70 C (PEF 2266: -40 C to +85 C);
Parameter Input voltages: Low level High level Output voltages: Low level Low level High level High level High level Input leakage current Symbol Limit Values min. -0.3 2.0 0.45 0.8 4.4 4.0 2.4 1 max. 0.8 Unit Test Condition
VIL VIH VOL VOL VOH VOH VOH VIL
V V V V V V V A
IOL = - 2 mA IOL = - 5 mA IOH = 0.4 mA IOH = 2 mA IOH = 5 mA -0.3 VIN VDD
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Electrical Characteristics and Timing Diagrams
8.4
Analog Interface
VDD = 5 V 5%; GNDD = 0 V; GNDA = 0 V; TA = 0 C to +70 C (PEF 2266: -40 C to +85 C)
Parameter Input resistance PEF 2266 PEB 2266 Output resistance Output load Input leakage current Input offset voltage Output offset voltage Input voltage range (AC) Symbol Limit Values min. 160 160 typ. 270 270 max. 500 380 0.25 300 50 0.1 1.0 50 50 2.223 Unit Test Condition 0 VIN VDD
Ri
k k pF A mV mV V
RO RL CL IIL VIO VOO VIN
0 VIN VDD
8.4.1
Coupling Capacitors at the Analog Interface
Coupling capacitors are required on pins VIN and VOUT. The recommended value for VIN is >39 nF. The required value for the VOUT capacitor depends on the input impedance of the SLIC (see Figure 16 in Chapter 5.1).
8.5
Reset Timing
To reset the SICOFI(R)2-C to Reset State, logic low pulses applied to pin RESET# must be below 1.2 V (TTL-Schmitt-Trigger Input) and must persist longer than 3 s. Note: Spikes shorter than 1 s will be ignored.
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Electrical Characteristics and Timing Diagrams
8.6 8.6.1
PCM-Interface Timing Single Clocking Mode
t PCLK PCLK 50% t FSC t FSC_S FSC t DR_S t DR_H DRA/B t dDX t dDXhz High Imp. DXA/B tdTCon t dTCoff t FSC_H t PCLKh
TCA#/TCB#
2266_229
Figure 29 Parameter
PCM Interface Timing in Single Clocking Mode Symbol min. Limit Values typ. max. 1/128 ms s s ns ns ns ns 0.6*tPCLK 1/8192 0.4*tPCLK 10 40 10 10 25 25 25 25 Unit
Period of PCLK PCLK high time Period FSC FSC setup time FSC hold time DRA/B setup time DRA/B hold time DXA/B delay time 1) DXA/B delay time to high Z TCA#/TCB# delay time on TCA#/TCB# delay time off
1)
tPCLK tPCLKh tFSC tFSC_s tFSC_h tDR_s tDR_h tdDX tdDXhz tdTCon tdTCoff
tPCLK/2
125 50 50 50 50
tdDX_min + tC_Load
50
ns ns ns ns
tdTCon_min + tC_Load tdTCoff_min + tC*R
Min. delay times: intrinsic time, caused by internal processing. Max. delay times: min. time + delay caused by external components CLoad and RPullup.: tC_Load = 0.4ns*CLoad/pF, tC*R = RPullup*CLoad; RPullup>1.5k
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Electrical Characteristics and Timing Diagrams
8.6.2
Double Clocking Mode
t PCLK PCLK 50%
t PCLKh
t FSC t FSC_S FSC t DR_S t DR_H t FSC_H
DRA/B t dDX t dDXhz High Imp. DXA/B t dTCon t dDTCoff
TCA#/TCB#
2266_230
Figure 30 Parameter
PCM Interface Timing in Double Clocking Mode Symbol min. Limit Values typ. max. 1/256 ms s s ns ns ns ns 0.6*tPCLK 1/8192 0.4*tPCLK 10 40 10 10 25 25 25 25 Unit
Period of PCLK PCLK high time Period FSC FSC setup time FSC hold time DRA/B setup time DRA/B hold time DXA/B delay time 1) DXA/B delay time to high Z TCA#/TCB# delay time on TCA#/TCB# delay time off
1)
tPCLK tPCLKh tFSC tFSC_s tFSC_h tDR_s tDR_h tdDX tdDXhz tdTCon tdTCoff
tPCLK/2
125 50 50 50 50
tdDX_min + tC_Load
50
ns ns ns ns
tdTCon_min + tC_Load tdTCoff_min + tC*R
Min. delay times: intrinsic time, caused by internal processing. Max. delay times: min. time + delay caused by external components CLoad and RPullup.: tC_Load = 0.4ns*CLoad/pF, tC*R = RPullup*CLoad; RPullup>1.5k
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Electrical Characteristics and Timing Diagrams
8.7
Microcontroller Interface Timing
t DCLK DCLK
50%
t DCLKh
t CS_S
t CS_h
CS# t DIN_S t DIN_H
DIN t dDOUT t dDOUThz High Imp. DOUT
2266_231
Figure 31
Timing of the Microcontroller Interface
Parameter Period of DCLK DCLK high time CS# setup time CS# hold time DIN setup time DIN hold time DOUT delay time 1) DOUT delay time to high Z
1)
Symbol min.
Limit Values typ. max. 1/8192 0.4*tDCLK tDCLK/2 10 30 10 10 30 30 50 50 50 50 0.6*tDCLK
Unit ms s ns ns ns ns
tDCLK tDCLKh tCS_s tCS_h tDIN_s tDIN_h tdDOUT tdDOUThz
tdDOUT_min + tC_Load
50
ns ns
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing, and a second component tC_Load = 0.4ns*CLoad/pF, caused by external circuitry (C-load).
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Electrical Characteristics and Timing Diagrams
8.8 8.8.1
Signaling Interface Timing Timing from the C Interface to the SO/SB-pins
DCLK
DIN
Bit 2
Bit 1
Bit 0 t dSout
SO/SB Output
Old Value t dSBZ
New Value
SB (Output
High Imp. Input) t dSBD
SB (Input
High Imp. Output)
2266_232
Figure 32 Parameter
Signaling Output Timing (data downstream) Symbol min. Limit Values typ. max. 30 40 40 Unit ns ns ns
SO/SB delay time 1) SB to `Z' - time SB to `drive'-time
1)
tdSout tdSBZ tdSBD
tdSout_min+ tC_Load
100
tdSBD_min+ tC_Load
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing, and a second component tC_Load = 0.4ns*CLoad/pF, caused by external circuitry (C-load).
8.8.2
Timing from the SI/SB-pins to the C Interface
The register update and interrupt behavior resulting from signaling input changes (data upstream - pins SI and SB, if programmed as signaling inputs) depend on internal sampling clocks, counters and register settings. See Chapter 5.3.2 for a functional description.
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Test Modes
9
Test Modes
Each SICOFI(R)2-C channel has four test loops that feed the analog input signal back to the analog output (analog test loops), and five test loops that feed the PCM input signal back to the PCM output. Note: The signal path can also be cut off at two different points per receive and transmit direction.
9.1
Analog Loops
The four analog loops feed signals from the transmit path back into the receive path. Figure 33 shows the locations of the analog loops.
Transmit Path
Analog
AGX
Input
ADC
Digital Gain 2
Frequency Response Digital Gain 1
HPX
CMP
PCM Output
ALB-PCM
ALB-PFI
ALB-4M
ALB-8K
IM2
IM1
TH
Analog
AGR
Output
DAC
Digital Gain 2
Frequency Response Digital Gain 1
HPR
EXP
PCM Input
Receive Path
2266_233
Figure 33 Table 34
Analog Loops Analog Loop Programming in Register CR3, Bits 7 to 4
Test-Loops Analog Loops (CR3.7 = 0) 0000 0001 0011 0100 All loops are disabled (normal operation). ALB-PFI ALB-4M ALB-PCM Analog Loop Back via PREFI-POFI is selected. Analog Loop Back via 4 MHz is selected. Analog Loop Back via 8 kHz (PCM) is selected and in all channels active. (required slope setting in XR6.6, XR6.5 = 00 or 11). Analog Loop Back via 8 kHz (linear) is selected.
0101
ALB-8K
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Test Modes
9.2
Digital Loops
The digital loops feed signals from the receive path back to the transmit path. There are five digital loops, which are shown in Figure 34.
Transmit Path
Analog
AGX
Input
ADC
Digital Gain 2
Frequency Response Digital Gain 1
HPX
CMP
PCM Output
DLB-128K
DLB-ANA
IM2
IM1
TH
Analog
AGR
Output
DAC
Digital Gain 2
Frequency Response Digital Gain 1
HPR
EXP
PCM Input
Receive Path
2266_234
Figure 34 Table 35
Digital Loops Digital Loop Programming in Register CR3, Bits 7 to 4
Test-Loops Digital Loops (CR3.7 = 1) 1000 1001 1100 1101 1111 DLB-ANA DLB-4M DLB-128K DLB-64K DLB-PCM Digital Loop Back via analog port is selected. Digital Loop Back via 4 MHz is selected. Digital Loop Back via 128 kHz is selected. Digital Loop Back via 64 kHz is selected. Digital Loop Back via PCM Registers is selected.
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DLB-PCM
DLB-64K
DLB-4M
PEB 2266 PEF 2266
Test Modes
9.3
Cut-Off's
The transmit path and the receive path can be cut off at two locations each. Figure 35 shows the locations in the signal paths.
Transmit Path
Analog
COT16 AGX ADC Digital Gain 2
Input
Frequency Response Digital Gain 1
COT8 HPX CMP
PCM Output
IM2
IM1
TH
COR4M
Analog
COR64 DAC Digital Gain 2
AGR
Output
Frequency Response Digital Gain 1
HPR
EXP
PCM Input
Receive Path
2266_235
Figure 35 Table 36 COT/R 000 001 010
Cut-Off's Cut-Off Programming in Register CR2, Bits 7 to 5. Cut-Off's in the Transmit and the Receive Paths All Cut-offs disabled (Normal Operation). COT16 COT8 Cut Off Transmit path at 16 kHz (input of TH-Filter). Cut Off Transmit path at 8 kHz (shortens the input of the compressor unit to ground, resulting in PCM idle codes in the transmit time slot). Cut Off Receive path at 4 MHz (POFI-output). Cut Off Receive path at 64 kHz (IM-filter input).
101 110
COR4M COR64
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Package Outlines
10
Package Outlines
P-MQFP-64 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information".
SMD = Surface Mounted Device Hardware Reference Manual 54
Dimensions in mm
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Glossary
11
AC ADC CMOS CRAM DAC DC DLC DSP DTMF FIR FTTC IIR IOM-2 ITU ITU-T PBX PCM PSTN PTT QSICOS RITL RT SICOFI SLIC t/r
Glossary
Alternating Current Analog-to-Digital Converter Complementary Metal Oxide Semiconductor Coefficient RAM Digital-to-Analog Converter Direct Current Digital Loop Carrier Digital Signal Processor Dual Tone Multi Frequency Finite Impulse Response Fiber-To-The-Curb Infinite Impulse Response ISDN-Oriented Modular 2nd Generation International Telecommunication Union International Telecommunication Union-Telecommunication Standardization Sector (formerly CCITT) Private Branch Exchange Pulse Code Modulation Public Switched Telephone Network Post Telephone Telegraph Quad SICOFI Coefficient Software Radio-In-The-Loop Remote Terminal Signal Processor Codec Filter Subscriber Line Interface Circuit tip/ring
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Index Symbols
-Law . . . . . . . . . . . . . . . 2, 11, 14, 19, 30 -Law mode . . . . . . . . . . . . . . . . . . 15, 22
AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Architecture . . . . . . . . . . . . . . . . . . . . . . 2 Attenuation . . . . . . . . . . . . . . . . . . . . . 18 AX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
B
Balancing filter . . . . . . . . . . . . . . . . . . . 26 Bi-directional signaling pins . . . . . . . 8, 33 Blocking capacitors . . . . . . . . . . . . . . . 42 Board design . . . . . . . . . . . . . . . . . . . . 42 Board layout . . . . . . . . . . . . . . . . . . . . 43 Byte-by-byte transfer . . . . . . . . . . . . . . 36
Numerics
0 dBm0-Levels . . . . . . . . . . . . . . . . . . . 14 2-wire to 4-wire conversion. . . . . . . . . . 10 8-bit time slots. . . . . . . . . . . . . . . . . . . . . 2
A
A/-Law. . . . . . . . . . . . . . . . . . . . . . . . . . 3 A/D and D/A converters . . . . . . 11, 18, 26 A/D converters . . . . . . . . . . . . . . . . 14, 23 Absolute gain . . . . . . . . . . . . . . . . . . . . 17 Absolute group delay . . . . . . . . . . . . . . 18 Absolute maximum ratings . . . . . . . . . . 44 AC transmission characteristics . . . . . . 27 Accuracy of digital filters . . . . . . . . . 10, 11 ADC . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 11 A-Law . . . . . . . . . . . . . . . 2, 11, 14, 19, 30 A-Law mode . . . . . . . . . . . . . . . . . . . . . 15 Ambient temperature . . . . . . . . . . . . . . 44 Analog ground pins. . . . . . . . . . . . 8, 9, 29 Analog I/O. . . . . . . . . . . . . . . . . . . . . . . . 2 Analog input . . . . . . . . . . . . . . . . . . . . . 13 Analog input/output pins . . . . . . . . . . . . 29 Analog Interface . . . . . . . . . . . . . 3, 27, 28 Analog interface . . . . . . . . . . . . . . . 14, 46 Analog Interface pins . . . . . . . . . . . . . . 29 Analog loop programming. . . . . . . . . . . 51 Analog loops . . . . . . . . . . . . . . . . . . . 3, 51 Analog output . . . . . . . . . . . . . . . . . . . . 13 Analog supply reference voltage . . . . . . 9 Analog supply voltage. . . . . . . . . . . . . . . 8 Analog voice input/output . . . . . . . . . . . . 8 Analog voltage levels . . . . . . . . . . . . . . 14 Application hints . . . . . . . . . . . . . . . . . . 41 Application Notes . . . . . . . . . . . . . . . . . . 1
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C
Ceramic capacitors . . . . . . . . . . . . . . . 42 Channel operating ranges . . . . . . . . . . 45 Channel-pair . . . . . . . . . . . . . . . . . . . . 33 Channels . . . . . . . . . . . . . . . . . . 2, 22, 37 Channel-specific coefficients . . . . . . . . 39 Channel-specific registers. . . .11, 12, 37, 38 Chip Select . . . . . . . . . . . . . . . . . . . 6, 34 Clock . . . . . . . . . . . . . . . . . 11, 32, 33, 34 Clock output signals . . . . . . . . . . . . . . . 2 Clock programming . . . . . . . . . . . . . . . 33 C-message . . . . . . . . . . . . . . . . . . . . . 19 Codec filter . . . . . . . . . . . . . . . . . . . . . . 2 Coefficient calculation & configuration software . . . . . . . . . . . . . . 3 Coefficient Operation (COP) command . .40 Coefficient operation commands . . . . . 39 Coefficient RAM. . . . . . 11, 34, 35, 37, 39 Command sequences . . . . . . . . . . 36, 40 Command type . . . . . . . . . . . . . . . . . . 40 Commands . . . . . . . . . . . . . . . . . . . . . 35 Common configuration registers . . . 11, 37, 38 Compression . . . . . . . . . . . . . . . . . . . . . 3 Compressor . . . . . . . . . . . . . . . . . . . . . 11 Configuration of interfaces. . . . . . . . . . 27 Configuration registers . . . . . . . . . 35, 37 Control Data input/output pins . . . . . . . 34
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Control data input/output pins. . . . . . . . 34 Conversion utilities . . . . . . . . . . . . . . . . 41 COP . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 COP command sequences. . . . . . . . . . 39 Country-specific adaptations . . . . . . . . 10 Coupling capacitors . . . . . . . . . 27, 29, 46 CR0 to CR5 . . . . . . . . . . . . . . . . . . . . . 37 CR0 to CR7 . . . . . . . . . . . . . . . . . . . . . 38 CRAM . . . . . . . . . . . 11, 34, 35, 37, 39, 40 CRAM structure . . . . . . . . . . . . . . . . . . 39 Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . 22 CR-Registers . . . . . . . . . . . . . . . . . . . . 11 CS#. . . . . . . . . . . . . . . . . . . . . . . . . 34, 49 Cut-Off programming . . . . . . . . . . . . . . 53 Cut-Off's . . . . . . . . . . . . . . . . . . . . . . . . 53
Digital, programmable filters . . . . . . . . 10 DIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Double clocking mode timing. . . . . . . . 48 DOUT . . . . . . . . . . . . . . . . . . . . . . . . . 49 Driving capability . . . . . . . . . . . . . . . 3, 27 DSP core . . . . . . . . . . . . . . . . 2, 3, 10, 11 DTMF. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Dynamic gain. . . . . . . . . . . . . . . . . . . . . 3 Dynamic range . . . . . . . . . . . . . . . . . . 11
E
EASY 2466 . . . . . . . . . . . . . . . . . . . 3, 41 EASY 2466 evaluation system . . . . . . 41 Echo . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Electrical characteristics . . . . . . . . . . . 44 Evaluation boards . . . . . . . . . . . . . . . . 41 EVC50x . . . . . . . . . . . . . . . . . . . . . . . . 41 Expander . . . . . . . . . . . . . . . . . . . . . . . 11 Expansion . . . . . . . . . . . . . . . . . . . . . . . 3 Extended Operation (XOP) command . . .40 Extended temperature range. . . . . . . . . 2 External amplifier. . . . . . . . . . . . . . . . . 27 External components. . . . . . . . . . . . . . 26
D
DAC . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 11 Data bytes. . . . . . . . . . . . . . . . . . . . . . . 35 Data Clock . . . . . . . . . . . . . . . . . . . . . . . 6 Data clock . . . . . . . . . . . . . . . . . . . . . . . 34 Data input pins . . . . . . . . . . . . . . . . . . . . 6 Data output pins . . . . . . . . . . . . . . . . . . . 6 Data pins. . . . . . . . . . . . . . . . . . . . . . . . 34 Data rates . . . . . . . . . . . . . . . . . . 3, 11, 30 Data receive pins . . . . . . . . . . . . . . . . . . 7 Data transmit pins. . . . . . . . . . . . . . . . . . 7 DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Debouncing functions . . . . . . . . . . . 32, 33 Decimation . . . . . . . . . . . . . . . . . . . . . . 11 Detect specific tones. . . . . . . . . . . . . . . 10 Development boards. . . . . . . . . . . . . 3, 41 Digital filters . . . . . . . . . . . . . . . . . . . . . . 3 Digital ground pins . . . . . . . . . . . . . . . . . 6 Digital input . . . . . . . . . . . . . . . . . . . . . . 13 Digital interface . . . . . . . . . . . . . . . . . . . 45 Digital loop programming . . . . . . . . . . . 52 Digital loops . . . . . . . . . . . . . . . . . . . 3, 52 Digital output. . . . . . . . . . . . . . . . . . . . . 13 Digital supply voltage . . . . . . . . . . . . . . . 7 Digital switching & transmission system . . . . 2
Hardware Reference Manual 57
F
Fiber-to-the-Curb Systems . . . . . . . . . . 4 Filter capacitors . . . . . . . . . . . . . . . . . . 42 Filter characteristics. . . . . . . . . . . . . . . 10 Filter coefficients . . . . . . . . . . . . . . . . . 27 Filter coefficients storage. . . . . . . . . . . 11 Filter structures . . . . . . . . . . . . . . . . . . 11 Flow diagram . . . . . . . . . . . . . . . . . . . . 16 Fluctuation . . . . . . . . . . . . . . . . . . . . . . 10 Four-wire interface. . . . . . . . . . . . . . . . 10 Frame . . . . . . . . . . . . . . . . . . . . . . . . . 30 Frame delay. . . . . . . . . . . . . . . . . . . . . 30 Frame synchronization clock . . . . . . 7, 30 Frequency correction. . . . . . . . . . . . . . 11 Frequency response . . . . . . . . . 3, 18, 27
2001-02-20
PEB 2266 PEF 2266
Frequency response corrections . . 10, 16 FRR . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 FRX. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 FSC. . . . . . . . . . . . . . . . . . . . . . . . . 47, 48 Functional blocks . . . . . . . . . . . . . . . . . 37
G
Gain . . . . . . . . . . . . . . . . . . . . . . . . 15, 26 Gain accuracy. . . . . . . . . . . . . . . . . . . . 17 Gain deviations with input level . . . . . . 17 Gain tracking. . . . . . . . . . . . . . . . . . . . . 17 Ground layer . . . . . . . . . . . . . . . . . . . . . 43 Ground pins . . . . . . . . . . . . . . . . . . . . . 43 Ground plane . . . . . . . . . . . . . . . . . . . . 43 Ground-key detection . . . . . . . . . . . . . . 10 Group delay . . . . . . . . . . . . . . . . . . 18, 26 Group delay absolute values . . . . . . . . 18 Group delay distortion. . . . . . . . . . . . . . 19
Input voltage range (AC) . . . . . . . . . . . 46 Input voltages . . . . . . . . . . . . . . . . . . . 45 INT12. . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interface description . . . . . . . . . . . . . . 27 Interfaces. . . . . . . . . . . . . . . . . . . . . . . 37 Intermodulation . . . . . . . . . . . . . . . . . . 20 Intermodulation distortion . . . . . . . . . . 20 Internal registers . . . . . . . . . . . . . . . . . 34 Interpolation. . . . . . . . . . . . . . . . . . . . . 11 Interrupt generation . . . . . . . . . . . . . . . 33 Interrupt output pins. . . . . . . . . . . . . . . 33 Interrupt pins . . . . . . . . . . . . . . . . . . . . 32 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 8 Inventory costs . . . . . . . . . . . . . . . . . . . 4 ITU-T . . . . . . . . . . . . . . . . . . . . . 3, 14, 16
K
Key Systems . . . . . . . . . . . . . . . . . . . . . 4
H
Hardware filters. . . . . . . . . . . . . . . . 11, 23 Hardware reset . . . . . . . . . . . . . . . . . . . 12 Harmonic distortion. . . . . . . . . . . . . . . . 20 High impedance state . . . . . . . . . . . . . . 34 Highway . . . . . . . . . . . . . . . . . . . . . . . . 11 HW-Reset . . . . . . . . . . . . . . . . . . . . . . . 12
L
Level adjustments . . . . . . . . . . . . . 10, 11 Level metering . . . . . . . . . . . . . . . . . 3, 10 Line characterization . . . . . . . . . . . . . . 10 Linearity . . . . . . . . . . . . . . . . . . . . . . 3, 11 Linecard functions . . . . . . . . . . . . . . . . 10 Load capacities . . . . . . . . . . . . . . . . . . 14 Local requirements . . . . . . . . . . . . . . . 10 Loop filters . . . . . . . . . . . . . . . . . . . . . . 10
I
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . 32 Identification byte . . . . . . . . . . . . . . . . . 35 Idle channel noise. . . . . . . . . . . . . . . . . 19 IM-filter . . . . . . . . . . . . . . . . . . . . . . 26, 39 Impedance matching . . . . . . 3, 10, 11, 16 Independent filter structures . . . . . . . . . . 2 Industry-standard PCM Interface . . . . . 30 Input impedance . . . . . . . . . . . . 10, 29, 46 Input leakage current . . . . . . . . . . . 45, 46 Input offset voltage . . . . . . . . . . . . . . . . 46 Input pins . . . . . . . . . . . . . . . . . . . . 12, 32 Input resistance . . . . . . . . . . . . . . . 27, 46
Hardware Reference Manual 58
M
Manufacturing test . . . . . . . . . . . . . . . . . 3 Master clock . . . . . . . . . . . . . . . . . . 7, 33 Maximum signal levels . . . . . . . . . . . . 14 Measurements. . . . . . . . . . . . . . . . . . . 41 Microcontroller . . . . . . . . . . . . . . . . . . . 10 Microcontroller Interface . . 10, 34, 39, 40 Microcontroller interface timing . . . . . . 49 Microcontrollers . . . . . . . . . . . . . . . . . . 27
2001-02-20
PEB 2266 PEF 2266
N
Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Noise rejection . . . . . . . . . . . . . . . . . . . 42 Non usable input. . . . . . . . . . . . . . . . . . . 6 Non usable input/output . . . . . . . . . . . . . 6 Not connected pins . . . . . . . . . . . . . . . 6, 9
O
On-/off-hook detection . . . . . . . . . . . . . 10 Operating conditions. . . . . . . . . . . . . . . 16 Operating range . . . . . . . . . . . . . . . . . . 45 Operating state . . . . . . . . . . . . . . . . 12, 13 Operating states . . . . . . . . . . . . . . . . . . 12 Operation of interfaces . . . . . . . . . . . . . 27 Operational description. . . . . . . . . . . . . 12 Optimization . . . . . . . . . . . . . . . . . . . . . 41 Out-of-band discrimination . . . . . . . 23, 24 Out-of-band idle channel noise. . . . . . . 25 Out-of-band signals . . . . . . . . . 23, 24, 27 Output load . . . . . . . . . . . . . . . . . . . . . . 46 Output offset voltage. . . . . . . . . . . . . . . 46 Output resistance . . . . . . . . . . . . . . . . . 46 Output voltages. . . . . . . . . . . . . . . . . . . 45 Overload compression . . . . . . . . . . . . . 22 Overload point . . . . . . . . . . . . . 14, 22, 27 Oversampling . . . . . . . . . . . . . . . . . . . . 11
P
Package . . . . . . . . . . . . . . . . . . . . . . . . . 3 Package Outlines . . . . . . . . . . . . . . . . . 54 Pair-Gain Systems . . . . . . . . . . . . . . . . . 4 PCLK . . . . . . . . . . . . . . . . . . . . . . . 47, 48 PCM clock. . . . . . . . . . . . . . . . . . . . . . . 30 PCM data clock. . . . . . . . . . . . . . . . . . . . 7 PCM data format. . . . . . . . . . . . . . . . . . 30 PCM Highway A . . . . . . . . . . . . . . . . . . . 7 PCM Highway B . . . . . . . . . . . . . . . . . . . 7 PCM highways . . . . . . . . . . . . 2, 3, 27, 30 PCM interface . . . . . . . . . . . . . . . 3, 14, 27 PCM interface pins . . . . . . . . . . . . . . . . 30
Hardware Reference Manual 59
PCM interface timing . . . . . . . . . . . 47, 48 PCM ports . . . . . . . . . . . . . . . . . . . . . . 11 Peak amplitude . . . . . . . . . . . . . . . 14, 27 PEB 2466 . . . . . . . . . . . . . . . . . . . . . . . 1 Pin configuration . . . . . . . . . . . . . . . . . . 5 Pin definitions and functions . . . . . . . . . 6 Pin descriptions . . . . . . . . . . . . . . . . . . . 5 Pin diagram . . . . . . . . . . . . . . . . . . . . . . 5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power dissipation . . . . . . . . . . . . . 12, 13 Power dissipation (package) . . . . . . . . 44 Power On. . . . . . . . . . . . . . . . . . . . . . . 12 Power spectral density . . . . . . . . . . . . 25 Power supply rejection ratio . . . . . . . . 45 Power-saving state . . . . . . . . . . . . . . . 12 POWER-UP state . . . . . . . . . . . . . . . . 33 Product Brief . . . . . . . . . . . . . . . . . . . . . 1 Product Overview . . . . . . . . . . . . . . . . . 1 Programmable debouncing . . . . . . . . . . 3 Programmable digital filters . . . . . . . . . . 3 Programmable filters . . . . . . . . . . . . . . 26 Programmable frequency . . . . . . . . . . 13 Programmable tone generators. . . . . . . 3 Programmer's Reference Manual . . . . . 1 Programming overview . . . . . . . . . . . . 37 PSB 2132 . . . . . . . . . . . . . . . . . . . . . . . 1 PSB 2134 . . . . . . . . . . . . . . . . . . . . . . . 1 Psophometric. . . . . . . . . . . . . . . . . . . . 19
Q
QSICOS. . . . . . . . . . . . . . . . . . . . . . 3, 41
R
Radio-in-the-Loop Systems . . . . . . . . . . 4 Read access . . . . . . . . . . . . . . . . . 35, 38 Read commands . . . . . . . . . . . . . . 35, 36 Receive data input pins . . . . . . . . . . . . 30 Receive delay . . . . . . . . . . . . . . . . . . . 18 Receive path . . . . . . . . . . . 10, 51, 52, 53 Reference voltage pin . . . . . . . . . . . 9, 29
2001-02-20
PEB 2266 PEF 2266
Register maps. . . . . . . . . . . . . . . . . . . . 38 Register model . . . . . . . . . . . . . . . . . . . 37 Register values . . . . . . . . . . . . . . . . . . . 13 Registers. . . . . . . . . . . . . . . . . . . . . . . . 11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Reset state . . . . . . . . . . . . . . . . 12, 13, 46 Reset timing . . . . . . . . . . . . . . . . . . . . . 46 RESET# . . . . . . . . . . . . . . . . . . . . . . . . 12 RESET# pin . . . . . . . . . . . . . . . . . . . . . 46 Resolution. . . . . . . . . . . . . . . . . . . . . . . 11 Return loss . . . . . . . . . . . . . . . . . . . . . . 10 Ring signals . . . . . . . . . . . . . . . . . . . . . 10 RITL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 RST. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
S
Sampling. . . . . . . . . . . . . . . . . . . . . . . . 34 Sampling intervals . . . . . . . . . . . . . . . . 33 Sampling slopes . . . . . . . . . . . . . . . . . . 30 Schmitt-Trigger input . . . . . . . . . . . . . . 46 Serial input . . . . . . . . . . . . . . . . . . . . . . 13 Serial Interface . . . . . . . . . . . . . . . . . . . . 2 Serial Microcontroller Interface . . 10, 27, 34 Serial output . . . . . . . . . . . . . . . . . . . . . 13 Sigma-delta. . . . . . . . . . . . . . . . . . . . . . 11 Signal levels . . . . . . . . . . . . . . . . . . . 3, 15 Signal paths . . . . . . . . . . . . . . . . . . . . . 53 Signal power transfer . . . . . . . . . . . . . . 10 Signal processor . . . . . . . . . . . . . . . . . . 10 Signal reflections . . . . . . . . . . . . . . . . . 10 Signal rejection . . . . . . . . . . . . . . . . . . . 23 Signaling example . . . . . . . . . . . . . . . . 32 Signaling input pins. . . . . . . . . . . . . . 8, 33 Signaling input/output pins . . . . . . . . . . 11 Signaling Interface . . . . . . . . . . 10, 27, 32 Signaling Interface pins . . . . . . . . . . . . 33 Signaling interface timing . . . . . . . . . . . 50 Signaling output pins . . . . . . . . . . . . 8, 33 Signaling output timing . . . . . . . . . . . . . 50 Signaling pins . . . . . . . . . . . . . . . . . . 2, 32 Signaling registers . . . . . . . . . . . . . . . . 33
Hardware Reference Manual 60
Signaling status changes. . . . . . . . . . . 32 Signal-to-noise performance . . . . . . . . 11 Signal-to-total distortion ratio. . . . . 20, 21 Sine wave signal . . . . . . . . . . . . . . . . . 14 Single clocking mode timing . . . . . . . . 47 Single frequency distortion . . . . . . . . . 22 SLIC. . . . . . . . . . . . . . 2, 3, 10, 16, 26, 27 SLIC daughter cards . . . . . . . . . . . . . . 41 SLIC interfaces . . . . . . . . . . . . . . . . . . 33 SOP . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Specifications . . . . . . . . . . . . . . . . . . . 16 Spikes . . . . . . . . . . . . . . . . . . . . . . . . . 46 Standard temperature range . . . . . . . . . 2 Standby operating range . . . . . . . . . . . 45 Standby state. . . . . . . . . . . . . . . . . 12, 13 State diagram . . . . . . . . . . . . . . . . . . . 12 States . . . . . . . . . . . . . . . . . . . . . . 12, 13 Status Operation (SOP) command . . . 40 Storage temperature . . . . . . . . . . . . . . 44 Subscriber line interface circuits . . . 2, 10, 27 Subscriber lines . . . . . . . . . . . . . . . . . . 32 Supervision and signaling functions . . 32 Supply current . . . . . . . . . . . . . . . . . . . 45 Supply voltage . . . . . . . . . . . . . . . . . . . . 3 Supply voltage pins . . . . . . . . . . . . . . . 29 Support tools . . . . . . . . . . . . . . . . . . 3, 41 SW-Reset . . . . . . . . . . . . . . . . . . . . . . 12 System diagnostics . . . . . . . . . . . . . . . . 3 System tests . . . . . . . . . . . . . . . . . . . . . 3
T
Tantalum capacitors . . . . . . . . . . . . . . 42 Telco specification . . . . . . . . . . . . . . . . 27 Telephone line . . . . . . . . . . . . . . . . . . . 27 Telephone linecard . . . . . . . . . . . . . . . 10 Telephone subscriber loop . . . . . . . . . 10 Teletax filters . . . . . . . . . . . . . . . . . . . . 27 Teletax pulses . . . . . . . . . . . . . . . . 23, 27 Test circuit . . . . . . . . . . . . . . . . . . . . . . 42 Test conditions . . . . . . . . . . . . . . . . . . 16 Test loops . . . . . . . . . . . . . . . . . . . 26, 51
2001-02-20
PEB 2266 PEF 2266
Test modes . . . . . . . . . . . . . . . . . . . . . . 51 Test relays . . . . . . . . . . . . . . . . . . . . . . 10 TG1 and TG2 . . . . . . . . . . . . . . . . . . . . 39 TH-filter . . . . . . . . . . . . . . . . . . . . . . 37, 39 Three-Wire access . . . . . . . . . . . . . . . . 36 Time slot assignment . . . . . . . . . . . . 3, 11 Time slots . . . . . . . . . . . . . . . . . . . . . 2, 30 Time to market . . . . . . . . . . . . . . . . . . . . 4 Timing . . . . . . . . . . . . . . . . . . . . 47, 49, 50 Timing diagrams . . . . . . . . . . . . . . . . . . 44 Tip & ring . . . . . . . . . . . . . . . . . . . . . . . 27 Tone generators . . . . . . . . . . . . . . . . 3, 10 Tool package . . . . . . . . . . . . . . . . . . . . 41 Total distortion receive/transmit . . . 20, 21 Total gain calculation . . . . . . . . . . . . . . 15 Transfer functions . . . . . . . . . . . . . . . . . 27 Transformer . . . . . . . . . . . . . . . . 3, 10, 27 Transformer SLIC . . . . . . . . . . . . . . . . . 27 Transhybrid balancing . . 3, 10, 11, 16, 26 Transhybrid loss . . . . . . . . . . . . . . . 10, 26 Transmission characteristics. . . 10, 14, 16, 37 Transmission system . . . . . . . . . . . . . . 41 Transmit control output pins . . . . . . . . . 30 Transmit control pins . . . . . . . . . . . . . . . 7 Transmit data output pins . . . . . . . . . . . 30 Transmit delay . . . . . . . . . . . . . . . . . . . 18 Transmit path . . . . . . . . . . . 10, 51, 52, 53 Two-wire interface . . . . . . . . . . . . . . . . 10 Types of commands . . . . . . . . . . . . . . . 40
Write commands . . . . . . . . . . . . . . 35, 36
X
XOP . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 XR0 to XR7 . . . . . . . . . . . . . . . . . . . . . 38 XR-Registers . . . . . . . . . . . . . . . . . . . . 11
V
VIN-pins . . . . . . . . . . . . . . . . . . . . . . . . 27 Voice channels . . . . . . . . . . . . . . . . . . . 11 Voltage levels . . . . . . . . . . . . . . . . . . . . 12 VOUT-pins . . . . . . . . . . . . . . . . . . . . . . 27
W
Waiting time . . . . . . . . . . . . . . . . . . . . . 36 Website. . . . . . . . . . . . . . . . . . . . . . . . . . 1 Write access . . . . . . . . . . . . . . . . . . 35, 38
Hardware Reference Manual 61 2001-02-20
Infineon goes for Business Excellence
"Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction."
Dr. Ulrich Schumacher
http://www.infineon.com
Published by Infineon Technologies AG


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